1 /* 2 * (C) Copyright 2010-2011 3 * NVIDIA Corporation <www.nvidia.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 #include <asm/types.h> 24 25 /* Stabilization delays, in usec */ 26 #define PLL_STABILIZATION_DELAY (300) 27 #define IO_STABILIZATION_DELAY (1000) 28 29 #define NVBL_PLLP_KHZ (216000) 30 31 #define PLLX_ENABLED (1 << 30) 32 #define CCLK_BURST_POLICY 0x20008888 33 #define SUPER_CCLK_DIVIDER 0x80000000 34 35 /* Calculate clock fractional divider value from ref and target frequencies */ 36 #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) 37 38 /* Calculate clock frequency value from reference and clock divider value */ 39 #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) 40 41 /* AVP/CPU ID */ 42 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */ 43 #define PG_UP_TAG_0 0x0 44 45 #define CORESIGHT_UNLOCK 0xC5ACCE55; 46 47 /* AP20-Specific Base Addresses */ 48 49 /* AP20 Base physical address of SDRAM. */ 50 #define AP20_BASE_PA_SDRAM 0x00000000 51 /* AP20 Base physical address of internal SRAM. */ 52 #define AP20_BASE_PA_SRAM 0x40000000 53 /* AP20 Size of internal SRAM (256KB). */ 54 #define AP20_BASE_PA_SRAM_SIZE 0x00040000 55 /* AP20 Base physical address of flash. */ 56 #define AP20_BASE_PA_NOR_FLASH 0xD0000000 57 /* AP20 Base physical address of boot information table. */ 58 #define AP20_BASE_PA_BOOT_INFO AP20_BASE_PA_SRAM 59 60 /* 61 * Super-temporary stacks for EXTREMELY early startup. The values chosen for 62 * these addresses must be valid on ALL SOCs because this value is used before 63 * we are able to differentiate between the SOC types. 64 * 65 * NOTE: The since CPU's stack will eventually be moved from IRAM to SDRAM, its 66 * stack is placed below the AVP stack. Once the CPU stack has been moved, 67 * the AVP is free to use the IRAM the CPU stack previously occupied if 68 * it should need to do so. 69 * 70 * NOTE: In multi-processor CPU complex configurations, each processor will have 71 * its own stack of size CPU_EARLY_BOOT_STACK_SIZE. CPU 0 will have a 72 * limit of CPU_EARLY_BOOT_STACK_LIMIT. Each successive CPU will have a 73 * stack limit that is CPU_EARLY_BOOT_STACK_SIZE less then the previous 74 * CPU. 75 */ 76 77 /* Common AVP early boot stack limit */ 78 #define AVP_EARLY_BOOT_STACK_LIMIT \ 79 (AP20_BASE_PA_SRAM + (AP20_BASE_PA_SRAM_SIZE/2)) 80 /* Common AVP early boot stack size */ 81 #define AVP_EARLY_BOOT_STACK_SIZE 0x1000 82 /* Common CPU early boot stack limit */ 83 #define CPU_EARLY_BOOT_STACK_LIMIT \ 84 (AVP_EARLY_BOOT_STACK_LIMIT - AVP_EARLY_BOOT_STACK_SIZE) 85 /* Common CPU early boot stack size */ 86 #define CPU_EARLY_BOOT_STACK_SIZE 0x1000 87 88 #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100) 89 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0) 90 #define CSITE_CPU_DBG1_LAR (NV_PA_CSITE_BASE + 0x12FB0) 91 92 #define FLOW_CTLR_HALT_COP_EVENTS (NV_PA_FLOW_BASE + 4) 93 #define FLOW_MODE_STOP 2 94 #define HALT_COP_EVENT_JTAG (1 << 28) 95 #define HALT_COP_EVENT_IRQ_1 (1 << 11) 96 #define HALT_COP_EVENT_FIQ_1 (1 << 9) 97 98 /* This is the main entry into U-Boot, used by the Cortex-A9 */ 99 extern void _start(void); 100 101 /** 102 * Works out the SOC type used for clocks settings 103 * 104 * @return SOC type - see TEGRA_SOC... 105 */ 106 int tegra_get_chip_type(void); 107