1 /* 2 * (C) Copyright 2007-2011 3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4 * Tom Cubie <tangliang@allwinnertech.com> 5 * 6 * Configuration settings for the Allwinner A10-evb board. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _SUNXI_TIMER_H_ 12 #define _SUNXI_TIMER_H_ 13 14 #define WDT_CTRL_RESTART (0x1 << 0) 15 #define WDT_CTRL_KEY (0x0a57 << 1) 16 #define WDT_MODE_EN (0x1 << 0) 17 #define WDT_MODE_RESET_EN (0x1 << 1) 18 19 #ifndef __ASSEMBLY__ 20 21 #include <linux/types.h> 22 23 /* General purpose timer */ 24 struct sunxi_timer { 25 u32 ctl; 26 u32 inter; 27 u32 val; 28 u8 res[4]; 29 }; 30 31 /* Audio video sync*/ 32 struct sunxi_avs { 33 u32 ctl; /* 0x80 */ 34 u32 cnt0; /* 0x84 */ 35 u32 cnt1; /* 0x88 */ 36 u32 div; /* 0x8c */ 37 }; 38 39 /* 64 bit counter */ 40 struct sunxi_64cnt { 41 u32 ctl; /* 0xa0 */ 42 u32 lo; /* 0xa4 */ 43 u32 hi; /* 0xa8 */ 44 }; 45 46 /* Watchdog */ 47 struct sunxi_wdog { 48 u32 ctl; /* 0x90 */ 49 u32 mode; /* 0x94 */ 50 }; 51 52 /* Rtc */ 53 struct sunxi_rtc { 54 u32 ctl; /* 0x100 */ 55 u32 yymmdd; /* 0x104 */ 56 u32 hhmmss; /* 0x108 */ 57 }; 58 59 /* Alarm */ 60 struct sunxi_alarm { 61 u32 ddhhmmss; /* 0x10c */ 62 u32 hhmmss; /* 0x110 */ 63 u32 en; /* 0x114 */ 64 u32 irqen; /* 0x118 */ 65 u32 irqsta; /* 0x11c */ 66 }; 67 68 /* Timer general purpose register */ 69 struct sunxi_tgp { 70 u32 tgpd; 71 }; 72 73 struct sunxi_timer_reg { 74 u32 tirqen; /* 0x00 */ 75 u32 tirqsta; /* 0x04 */ 76 u8 res1[8]; 77 struct sunxi_timer timer[6]; /* We have 6 timers */ 78 u8 res2[16]; 79 struct sunxi_avs avs; 80 struct sunxi_wdog wdog; 81 u8 res3[8]; 82 struct sunxi_64cnt cnt64; 83 u8 res4[0x58]; 84 struct sunxi_rtc rtc; 85 struct sunxi_alarm alarm; 86 struct sunxi_tgp tgp[4]; 87 u8 res5[8]; 88 u32 cpu_cfg; 89 }; 90 91 #endif /* __ASSEMBLY__ */ 92 93 #endif 94