1 /* 2 * (C) Copyright 2007-2011 3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4 * Aaron <leafy.myeh@allwinnertech.com> 5 * 6 * MMC register definition for allwinner sunxi platform. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _SUNXI_MMC_H 12 #define _SUNXI_MMC_H 13 14 #include <linux/types.h> 15 16 struct sunxi_mmc { 17 u32 gctrl; /* 0x00 global control */ 18 u32 clkcr; /* 0x04 clock control */ 19 u32 timeout; /* 0x08 time out */ 20 u32 width; /* 0x0c bus width */ 21 u32 blksz; /* 0x10 block size */ 22 u32 bytecnt; /* 0x14 byte count */ 23 u32 cmd; /* 0x18 command */ 24 u32 arg; /* 0x1c argument */ 25 u32 resp0; /* 0x20 response 0 */ 26 u32 resp1; /* 0x24 response 1 */ 27 u32 resp2; /* 0x28 response 2 */ 28 u32 resp3; /* 0x2c response 3 */ 29 u32 imask; /* 0x30 interrupt mask */ 30 u32 mint; /* 0x34 masked interrupt status */ 31 u32 rint; /* 0x38 raw interrupt status */ 32 u32 status; /* 0x3c status */ 33 u32 ftrglevel; /* 0x40 FIFO threshold watermark*/ 34 u32 funcsel; /* 0x44 function select */ 35 u32 cbcr; /* 0x48 CIU byte count */ 36 u32 bbcr; /* 0x4c BIU byte count */ 37 u32 dbgc; /* 0x50 debug enable */ 38 u32 res0[11]; 39 u32 dmac; /* 0x80 internal DMA control */ 40 u32 dlba; /* 0x84 internal DMA descr list base address */ 41 u32 idst; /* 0x88 internal DMA status */ 42 u32 idie; /* 0x8c internal DMA interrupt enable */ 43 u32 chda; /* 0x90 */ 44 u32 cbda; /* 0x94 */ 45 u32 res1[26]; 46 #ifdef CONFIG_SUNXI_GEN_SUN6I 47 u32 res2[64]; 48 #endif 49 u32 fifo; /* 0x100 / 0x200 FIFO access address */ 50 }; 51 52 #define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) 53 #define SUNXI_MMC_CLK_ENABLE (0x1 << 16) 54 #define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) 55 56 #define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) 57 #define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) 58 #define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) 59 #define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ 60 SUNXI_MMC_GCTRL_FIFO_RESET|\ 61 SUNXI_MMC_GCTRL_DMA_RESET) 62 #define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) 63 #define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) 64 65 #define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) 66 #define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) 67 #define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) 68 #define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) 69 #define SUNXI_MMC_CMD_WRITE (0x1 << 10) 70 #define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) 71 #define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) 72 #define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) 73 #define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) 74 #define SUNXI_MMC_CMD_START (0x1 << 31) 75 76 #define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) 77 #define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) 78 #define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) 79 #define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) 80 #define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) 81 #define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) 82 #define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) 83 #define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) 84 #define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) 85 #define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) 86 #define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) 87 #define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) 88 #define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) 89 #define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) 90 #define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) 91 #define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) 92 #define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) 93 #define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) 94 #define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ 95 (SUNXI_MMC_RINT_RESP_ERROR | \ 96 SUNXI_MMC_RINT_RESP_CRC_ERROR | \ 97 SUNXI_MMC_RINT_DATA_CRC_ERROR | \ 98 SUNXI_MMC_RINT_RESP_TIMEOUT | \ 99 SUNXI_MMC_RINT_DATA_TIMEOUT | \ 100 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ 101 SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ 102 SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ 103 SUNXI_MMC_RINT_START_BIT_ERROR | \ 104 SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ 105 #define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ 106 (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ 107 SUNXI_MMC_RINT_DATA_OVER | \ 108 SUNXI_MMC_RINT_COMMAND_DONE | \ 109 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) 110 111 #define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) 112 #define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) 113 #define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) 114 #define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) 115 #define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) 116 #define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) 117 #define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) 118 119 #define SUNXI_MMC_IDMAC_RESET (0x1 << 0) 120 #define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) 121 #define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) 122 123 #define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) 124 #define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) 125 126 #define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) 127 #define SUNXI_MMC_COMMON_RESET (1 << 18) 128 129 struct mmc *sunxi_mmc_init(int sdc_no); 130 int sunxi_mmc_has_egon_boot_signature(struct mmc *mmc); 131 #endif /* _SUNXI_MMC_H */ 132