1 /*
2  * (C) Copyright 2007-2011
3  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4  * Aaron <leafy.myeh@allwinnertech.com>
5  *
6  * MMC register definition for allwinner sunxi platform.
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef _SUNXI_MMC_H
12 #define _SUNXI_MMC_H
13 
14 #include <linux/types.h>
15 
16 struct sunxi_mmc {
17 	u32 gctrl;		/* 0x00 global control */
18 	u32 clkcr;		/* 0x04 clock control */
19 	u32 timeout;		/* 0x08 time out */
20 	u32 width;		/* 0x0c bus width */
21 	u32 blksz;		/* 0x10 block size */
22 	u32 bytecnt;		/* 0x14 byte count */
23 	u32 cmd;		/* 0x18 command */
24 	u32 arg;		/* 0x1c argument */
25 	u32 resp0;		/* 0x20 response 0 */
26 	u32 resp1;		/* 0x24 response 1 */
27 	u32 resp2;		/* 0x28 response 2 */
28 	u32 resp3;		/* 0x2c response 3 */
29 	u32 imask;		/* 0x30 interrupt mask */
30 	u32 mint;		/* 0x34 masked interrupt status */
31 	u32 rint;		/* 0x38 raw interrupt status */
32 	u32 status;		/* 0x3c status */
33 	u32 ftrglevel;		/* 0x40 FIFO threshold watermark*/
34 	u32 funcsel;		/* 0x44 function select */
35 	u32 cbcr;		/* 0x48 CIU byte count */
36 	u32 bbcr;		/* 0x4c BIU byte count */
37 	u32 dbgc;		/* 0x50 debug enable */
38 	u32 res0;		/* 0x54 reserved */
39 	u32 a12a;		/* 0x58 Auto command 12 argument */
40 	u32 ntsr;		/* 0x5c	New timing set register */
41 	u32 res1[8];
42 	u32 dmac;		/* 0x80 internal DMA control */
43 	u32 dlba;		/* 0x84 internal DMA descr list base address */
44 	u32 idst;		/* 0x88 internal DMA status */
45 	u32 idie;		/* 0x8c internal DMA interrupt enable */
46 	u32 chda;		/* 0x90 */
47 	u32 cbda;		/* 0x94 */
48 	u32 res2[26];
49 #ifdef CONFIG_SUNXI_GEN_SUN6I
50 	u32 res3[64];
51 #endif
52 	u32 fifo;		/* 0x100 / 0x200 FIFO access address */
53 };
54 
55 #define SUNXI_MMC_CLK_POWERSAVE		(0x1 << 17)
56 #define SUNXI_MMC_CLK_ENABLE		(0x1 << 16)
57 #define SUNXI_MMC_CLK_DIVIDER_MASK	(0xff)
58 
59 #define SUNXI_MMC_GCTRL_SOFT_RESET	(0x1 << 0)
60 #define SUNXI_MMC_GCTRL_FIFO_RESET	(0x1 << 1)
61 #define SUNXI_MMC_GCTRL_DMA_RESET	(0x1 << 2)
62 #define SUNXI_MMC_GCTRL_RESET		(SUNXI_MMC_GCTRL_SOFT_RESET|\
63 					 SUNXI_MMC_GCTRL_FIFO_RESET|\
64 					 SUNXI_MMC_GCTRL_DMA_RESET)
65 #define SUNXI_MMC_GCTRL_DMA_ENABLE	(0x1 << 5)
66 #define SUNXI_MMC_GCTRL_ACCESS_BY_AHB   (0x1 << 31)
67 
68 #define SUNXI_MMC_CMD_RESP_EXPIRE	(0x1 << 6)
69 #define SUNXI_MMC_CMD_LONG_RESPONSE	(0x1 << 7)
70 #define SUNXI_MMC_CMD_CHK_RESPONSE_CRC	(0x1 << 8)
71 #define SUNXI_MMC_CMD_DATA_EXPIRE	(0x1 << 9)
72 #define SUNXI_MMC_CMD_WRITE		(0x1 << 10)
73 #define SUNXI_MMC_CMD_AUTO_STOP		(0x1 << 12)
74 #define SUNXI_MMC_CMD_WAIT_PRE_OVER	(0x1 << 13)
75 #define SUNXI_MMC_CMD_SEND_INIT_SEQ	(0x1 << 15)
76 #define SUNXI_MMC_CMD_UPCLK_ONLY	(0x1 << 21)
77 #define SUNXI_MMC_CMD_START		(0x1 << 31)
78 
79 #define SUNXI_MMC_RINT_RESP_ERROR		(0x1 << 1)
80 #define SUNXI_MMC_RINT_COMMAND_DONE		(0x1 << 2)
81 #define SUNXI_MMC_RINT_DATA_OVER		(0x1 << 3)
82 #define SUNXI_MMC_RINT_TX_DATA_REQUEST		(0x1 << 4)
83 #define SUNXI_MMC_RINT_RX_DATA_REQUEST		(0x1 << 5)
84 #define SUNXI_MMC_RINT_RESP_CRC_ERROR		(0x1 << 6)
85 #define SUNXI_MMC_RINT_DATA_CRC_ERROR		(0x1 << 7)
86 #define SUNXI_MMC_RINT_RESP_TIMEOUT		(0x1 << 8)
87 #define SUNXI_MMC_RINT_DATA_TIMEOUT		(0x1 << 9)
88 #define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE	(0x1 << 10)
89 #define SUNXI_MMC_RINT_FIFO_RUN_ERROR		(0x1 << 11)
90 #define SUNXI_MMC_RINT_HARD_WARE_LOCKED		(0x1 << 12)
91 #define SUNXI_MMC_RINT_START_BIT_ERROR		(0x1 << 13)
92 #define SUNXI_MMC_RINT_AUTO_COMMAND_DONE	(0x1 << 14)
93 #define SUNXI_MMC_RINT_END_BIT_ERROR		(0x1 << 15)
94 #define SUNXI_MMC_RINT_SDIO_INTERRUPT		(0x1 << 16)
95 #define SUNXI_MMC_RINT_CARD_INSERT		(0x1 << 30)
96 #define SUNXI_MMC_RINT_CARD_REMOVE		(0x1 << 31)
97 #define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT      \
98 	(SUNXI_MMC_RINT_RESP_ERROR |		\
99 	 SUNXI_MMC_RINT_RESP_CRC_ERROR |	\
100 	 SUNXI_MMC_RINT_DATA_CRC_ERROR |	\
101 	 SUNXI_MMC_RINT_RESP_TIMEOUT |		\
102 	 SUNXI_MMC_RINT_DATA_TIMEOUT |		\
103 	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE |	\
104 	 SUNXI_MMC_RINT_FIFO_RUN_ERROR |	\
105 	 SUNXI_MMC_RINT_HARD_WARE_LOCKED |	\
106 	 SUNXI_MMC_RINT_START_BIT_ERROR |	\
107 	 SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
108 #define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT	\
109 	(SUNXI_MMC_RINT_AUTO_COMMAND_DONE |	\
110 	 SUNXI_MMC_RINT_DATA_OVER |		\
111 	 SUNXI_MMC_RINT_COMMAND_DONE |		\
112 	 SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
113 
114 #define SUNXI_MMC_STATUS_RXWL_FLAG		(0x1 << 0)
115 #define SUNXI_MMC_STATUS_TXWL_FLAG		(0x1 << 1)
116 #define SUNXI_MMC_STATUS_FIFO_EMPTY		(0x1 << 2)
117 #define SUNXI_MMC_STATUS_FIFO_FULL		(0x1 << 3)
118 #define SUNXI_MMC_STATUS_CARD_PRESENT		(0x1 << 8)
119 #define SUNXI_MMC_STATUS_CARD_DATA_BUSY		(0x1 << 9)
120 #define SUNXI_MMC_STATUS_DATA_FSM_BUSY		(0x1 << 10)
121 
122 #define SUNXI_MMC_NTSR_MODE_SEL_NEW		(0x1 << 31)
123 
124 #define SUNXI_MMC_IDMAC_RESET		(0x1 << 0)
125 #define SUNXI_MMC_IDMAC_FIXBURST	(0x1 << 1)
126 #define SUNXI_MMC_IDMAC_ENABLE		(0x1 << 7)
127 
128 #define SUNXI_MMC_IDIE_TXIRQ		(0x1 << 0)
129 #define SUNXI_MMC_IDIE_RXIRQ		(0x1 << 1)
130 
131 #define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
132 #define SUNXI_MMC_COMMON_RESET			(1 << 18)
133 
134 struct mmc *sunxi_mmc_init(int sdc_no);
135 #endif /* _SUNXI_MMC_H */
136