1*e24ea55cSIan Campbell /* 2*e24ea55cSIan Campbell * (C) Copyright 2007-2011 3*e24ea55cSIan Campbell * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4*e24ea55cSIan Campbell * Aaron <leafy.myeh@allwinnertech.com> 5*e24ea55cSIan Campbell * 6*e24ea55cSIan Campbell * MMC register definition for allwinner sunxi platform. 7*e24ea55cSIan Campbell * 8*e24ea55cSIan Campbell * SPDX-License-Identifier: GPL-2.0+ 9*e24ea55cSIan Campbell */ 10*e24ea55cSIan Campbell 11*e24ea55cSIan Campbell #ifndef _SUNXI_MMC_H 12*e24ea55cSIan Campbell #define _SUNXI_MMC_H 13*e24ea55cSIan Campbell 14*e24ea55cSIan Campbell #include <linux/types.h> 15*e24ea55cSIan Campbell 16*e24ea55cSIan Campbell struct sunxi_mmc { 17*e24ea55cSIan Campbell u32 gctrl; /* 0x00 global control */ 18*e24ea55cSIan Campbell u32 clkcr; /* 0x04 clock control */ 19*e24ea55cSIan Campbell u32 timeout; /* 0x08 time out */ 20*e24ea55cSIan Campbell u32 width; /* 0x0c bus width */ 21*e24ea55cSIan Campbell u32 blksz; /* 0x10 block size */ 22*e24ea55cSIan Campbell u32 bytecnt; /* 0x14 byte count */ 23*e24ea55cSIan Campbell u32 cmd; /* 0x18 command */ 24*e24ea55cSIan Campbell u32 arg; /* 0x1c argument */ 25*e24ea55cSIan Campbell u32 resp0; /* 0x20 response 0 */ 26*e24ea55cSIan Campbell u32 resp1; /* 0x24 response 1 */ 27*e24ea55cSIan Campbell u32 resp2; /* 0x28 response 2 */ 28*e24ea55cSIan Campbell u32 resp3; /* 0x2c response 3 */ 29*e24ea55cSIan Campbell u32 imask; /* 0x30 interrupt mask */ 30*e24ea55cSIan Campbell u32 mint; /* 0x34 masked interrupt status */ 31*e24ea55cSIan Campbell u32 rint; /* 0x38 raw interrupt status */ 32*e24ea55cSIan Campbell u32 status; /* 0x3c status */ 33*e24ea55cSIan Campbell u32 ftrglevel; /* 0x40 FIFO threshold watermark*/ 34*e24ea55cSIan Campbell u32 funcsel; /* 0x44 function select */ 35*e24ea55cSIan Campbell u32 cbcr; /* 0x48 CIU byte count */ 36*e24ea55cSIan Campbell u32 bbcr; /* 0x4c BIU byte count */ 37*e24ea55cSIan Campbell u32 dbgc; /* 0x50 debug enable */ 38*e24ea55cSIan Campbell u32 res0[11]; 39*e24ea55cSIan Campbell u32 dmac; /* 0x80 internal DMA control */ 40*e24ea55cSIan Campbell u32 dlba; /* 0x84 internal DMA descr list base address */ 41*e24ea55cSIan Campbell u32 idst; /* 0x88 internal DMA status */ 42*e24ea55cSIan Campbell u32 idie; /* 0x8c internal DMA interrupt enable */ 43*e24ea55cSIan Campbell u32 chda; /* 0x90 */ 44*e24ea55cSIan Campbell u32 cbda; /* 0x94 */ 45*e24ea55cSIan Campbell u32 res1[26]; 46*e24ea55cSIan Campbell u32 fifo; /* 0x100 FIFO access address */ 47*e24ea55cSIan Campbell }; 48*e24ea55cSIan Campbell 49*e24ea55cSIan Campbell #define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) 50*e24ea55cSIan Campbell #define SUNXI_MMC_CLK_ENABLE (0x1 << 16) 51*e24ea55cSIan Campbell #define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) 52*e24ea55cSIan Campbell 53*e24ea55cSIan Campbell #define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) 54*e24ea55cSIan Campbell #define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) 55*e24ea55cSIan Campbell #define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) 56*e24ea55cSIan Campbell #define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ 57*e24ea55cSIan Campbell SUNXI_MMC_GCTRL_FIFO_RESET|\ 58*e24ea55cSIan Campbell SUNXI_MMC_GCTRL_DMA_RESET) 59*e24ea55cSIan Campbell #define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) 60*e24ea55cSIan Campbell #define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) 61*e24ea55cSIan Campbell 62*e24ea55cSIan Campbell #define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) 63*e24ea55cSIan Campbell #define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) 64*e24ea55cSIan Campbell #define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) 65*e24ea55cSIan Campbell #define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) 66*e24ea55cSIan Campbell #define SUNXI_MMC_CMD_WRITE (0x1 << 10) 67*e24ea55cSIan Campbell #define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) 68*e24ea55cSIan Campbell #define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) 69*e24ea55cSIan Campbell #define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) 70*e24ea55cSIan Campbell #define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) 71*e24ea55cSIan Campbell #define SUNXI_MMC_CMD_START (0x1 << 31) 72*e24ea55cSIan Campbell 73*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) 74*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) 75*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) 76*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) 77*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) 78*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) 79*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) 80*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) 81*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) 82*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) 83*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) 84*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) 85*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) 86*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) 87*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) 88*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) 89*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) 90*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) 91*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ 92*e24ea55cSIan Campbell (SUNXI_MMC_RINT_RESP_ERROR | \ 93*e24ea55cSIan Campbell SUNXI_MMC_RINT_RESP_CRC_ERROR | \ 94*e24ea55cSIan Campbell SUNXI_MMC_RINT_DATA_CRC_ERROR | \ 95*e24ea55cSIan Campbell SUNXI_MMC_RINT_RESP_TIMEOUT | \ 96*e24ea55cSIan Campbell SUNXI_MMC_RINT_DATA_TIMEOUT | \ 97*e24ea55cSIan Campbell SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ 98*e24ea55cSIan Campbell SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ 99*e24ea55cSIan Campbell SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ 100*e24ea55cSIan Campbell SUNXI_MMC_RINT_START_BIT_ERROR | \ 101*e24ea55cSIan Campbell SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ 102*e24ea55cSIan Campbell #define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ 103*e24ea55cSIan Campbell (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ 104*e24ea55cSIan Campbell SUNXI_MMC_RINT_DATA_OVER | \ 105*e24ea55cSIan Campbell SUNXI_MMC_RINT_COMMAND_DONE | \ 106*e24ea55cSIan Campbell SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) 107*e24ea55cSIan Campbell 108*e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) 109*e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) 110*e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) 111*e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) 112*e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) 113*e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) 114*e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) 115*e24ea55cSIan Campbell 116*e24ea55cSIan Campbell #define SUNXI_MMC_IDMAC_RESET (0x1 << 0) 117*e24ea55cSIan Campbell #define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) 118*e24ea55cSIan Campbell #define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) 119*e24ea55cSIan Campbell 120*e24ea55cSIan Campbell #define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) 121*e24ea55cSIan Campbell #define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) 122*e24ea55cSIan Campbell 123*e24ea55cSIan Campbell int sunxi_mmc_init(int sdc_no); 124*e24ea55cSIan Campbell #endif /* _SUNXI_MMC_H */ 125