183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2e24ea55cSIan Campbell /* 3e24ea55cSIan Campbell * (C) Copyright 2007-2011 4e24ea55cSIan Campbell * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 5e24ea55cSIan Campbell * Aaron <leafy.myeh@allwinnertech.com> 6e24ea55cSIan Campbell * 7e24ea55cSIan Campbell * MMC register definition for allwinner sunxi platform. 8e24ea55cSIan Campbell */ 9e24ea55cSIan Campbell 10e24ea55cSIan Campbell #ifndef _SUNXI_MMC_H 11e24ea55cSIan Campbell #define _SUNXI_MMC_H 12e24ea55cSIan Campbell 13e24ea55cSIan Campbell #include <linux/types.h> 14e24ea55cSIan Campbell 15e24ea55cSIan Campbell struct sunxi_mmc { 16e24ea55cSIan Campbell u32 gctrl; /* 0x00 global control */ 17e24ea55cSIan Campbell u32 clkcr; /* 0x04 clock control */ 18e24ea55cSIan Campbell u32 timeout; /* 0x08 time out */ 19e24ea55cSIan Campbell u32 width; /* 0x0c bus width */ 20e24ea55cSIan Campbell u32 blksz; /* 0x10 block size */ 21e24ea55cSIan Campbell u32 bytecnt; /* 0x14 byte count */ 22e24ea55cSIan Campbell u32 cmd; /* 0x18 command */ 23e24ea55cSIan Campbell u32 arg; /* 0x1c argument */ 24e24ea55cSIan Campbell u32 resp0; /* 0x20 response 0 */ 25e24ea55cSIan Campbell u32 resp1; /* 0x24 response 1 */ 26e24ea55cSIan Campbell u32 resp2; /* 0x28 response 2 */ 27e24ea55cSIan Campbell u32 resp3; /* 0x2c response 3 */ 28e24ea55cSIan Campbell u32 imask; /* 0x30 interrupt mask */ 29e24ea55cSIan Campbell u32 mint; /* 0x34 masked interrupt status */ 30e24ea55cSIan Campbell u32 rint; /* 0x38 raw interrupt status */ 31e24ea55cSIan Campbell u32 status; /* 0x3c status */ 32e24ea55cSIan Campbell u32 ftrglevel; /* 0x40 FIFO threshold watermark*/ 33e24ea55cSIan Campbell u32 funcsel; /* 0x44 function select */ 34e24ea55cSIan Campbell u32 cbcr; /* 0x48 CIU byte count */ 35e24ea55cSIan Campbell u32 bbcr; /* 0x4c BIU byte count */ 36e24ea55cSIan Campbell u32 dbgc; /* 0x50 debug enable */ 37de9b1771SMaxime Ripard u32 res0; /* 0x54 reserved */ 38de9b1771SMaxime Ripard u32 a12a; /* 0x58 Auto command 12 argument */ 39de9b1771SMaxime Ripard u32 ntsr; /* 0x5c New timing set register */ 40de9b1771SMaxime Ripard u32 res1[8]; 41e24ea55cSIan Campbell u32 dmac; /* 0x80 internal DMA control */ 42e24ea55cSIan Campbell u32 dlba; /* 0x84 internal DMA descr list base address */ 43e24ea55cSIan Campbell u32 idst; /* 0x88 internal DMA status */ 44e24ea55cSIan Campbell u32 idie; /* 0x8c internal DMA interrupt enable */ 45e24ea55cSIan Campbell u32 chda; /* 0x90 */ 46e24ea55cSIan Campbell u32 cbda; /* 0x94 */ 47de9b1771SMaxime Ripard u32 res2[26]; 48*42956f1bSIcenowy Zheng #if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) 49de9b1771SMaxime Ripard u32 res3[64]; 501d1bd42eSHans de Goede #endif 51daf22636SHans de Goede u32 fifo; /* 0x100 / 0x200 FIFO access address */ 52e24ea55cSIan Campbell }; 53e24ea55cSIan Campbell 54e24ea55cSIan Campbell #define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) 55e24ea55cSIan Campbell #define SUNXI_MMC_CLK_ENABLE (0x1 << 16) 56e24ea55cSIan Campbell #define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) 57e24ea55cSIan Campbell 58e24ea55cSIan Campbell #define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) 59e24ea55cSIan Campbell #define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) 60e24ea55cSIan Campbell #define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) 61e24ea55cSIan Campbell #define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ 62e24ea55cSIan Campbell SUNXI_MMC_GCTRL_FIFO_RESET|\ 63e24ea55cSIan Campbell SUNXI_MMC_GCTRL_DMA_RESET) 64e24ea55cSIan Campbell #define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) 65e24ea55cSIan Campbell #define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) 66e24ea55cSIan Campbell 67e24ea55cSIan Campbell #define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) 68e24ea55cSIan Campbell #define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) 69e24ea55cSIan Campbell #define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) 70e24ea55cSIan Campbell #define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) 71e24ea55cSIan Campbell #define SUNXI_MMC_CMD_WRITE (0x1 << 10) 72e24ea55cSIan Campbell #define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) 73e24ea55cSIan Campbell #define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) 74e24ea55cSIan Campbell #define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) 75e24ea55cSIan Campbell #define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) 76e24ea55cSIan Campbell #define SUNXI_MMC_CMD_START (0x1 << 31) 77e24ea55cSIan Campbell 78e24ea55cSIan Campbell #define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) 79e24ea55cSIan Campbell #define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) 80e24ea55cSIan Campbell #define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) 81e24ea55cSIan Campbell #define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) 82e24ea55cSIan Campbell #define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) 83e24ea55cSIan Campbell #define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) 84e24ea55cSIan Campbell #define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) 85e24ea55cSIan Campbell #define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) 86e24ea55cSIan Campbell #define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) 87e24ea55cSIan Campbell #define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) 88e24ea55cSIan Campbell #define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) 89e24ea55cSIan Campbell #define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) 90e24ea55cSIan Campbell #define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) 91e24ea55cSIan Campbell #define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) 92e24ea55cSIan Campbell #define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) 93e24ea55cSIan Campbell #define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) 94e24ea55cSIan Campbell #define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) 95e24ea55cSIan Campbell #define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) 96e24ea55cSIan Campbell #define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ 97e24ea55cSIan Campbell (SUNXI_MMC_RINT_RESP_ERROR | \ 98e24ea55cSIan Campbell SUNXI_MMC_RINT_RESP_CRC_ERROR | \ 99e24ea55cSIan Campbell SUNXI_MMC_RINT_DATA_CRC_ERROR | \ 100e24ea55cSIan Campbell SUNXI_MMC_RINT_RESP_TIMEOUT | \ 101e24ea55cSIan Campbell SUNXI_MMC_RINT_DATA_TIMEOUT | \ 102e24ea55cSIan Campbell SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ 103e24ea55cSIan Campbell SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ 104e24ea55cSIan Campbell SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ 105e24ea55cSIan Campbell SUNXI_MMC_RINT_START_BIT_ERROR | \ 106e24ea55cSIan Campbell SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ 107e24ea55cSIan Campbell #define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ 108e24ea55cSIan Campbell (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ 109e24ea55cSIan Campbell SUNXI_MMC_RINT_DATA_OVER | \ 110e24ea55cSIan Campbell SUNXI_MMC_RINT_COMMAND_DONE | \ 111e24ea55cSIan Campbell SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) 112e24ea55cSIan Campbell 113e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) 114e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) 115e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) 116e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) 117e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) 118e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) 119e24ea55cSIan Campbell #define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) 120e24ea55cSIan Campbell 121de9b1771SMaxime Ripard #define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31) 122de9b1771SMaxime Ripard 123e24ea55cSIan Campbell #define SUNXI_MMC_IDMAC_RESET (0x1 << 0) 124e24ea55cSIan Campbell #define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) 125e24ea55cSIan Campbell #define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) 126e24ea55cSIan Campbell 127e24ea55cSIan Campbell #define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) 128e24ea55cSIan Campbell #define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) 129e24ea55cSIan Campbell 130daf22636SHans de Goede #define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) 131daf22636SHans de Goede #define SUNXI_MMC_COMMON_RESET (1 << 18) 132daf22636SHans de Goede 133e79c7c88SHans de Goede struct mmc *sunxi_mmc_init(int sdc_no); 134e24ea55cSIan Campbell #endif /* _SUNXI_MMC_H */ 135