1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Sunxi platform timing controller register and constant defines 4 * 5 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> 6 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> 7 */ 8 9 #ifndef _LCDC_H 10 #define _LCDC_H 11 12 #include <fdtdec.h> 13 14 struct sunxi_lcdc_reg { 15 u32 ctrl; /* 0x00 */ 16 u32 int0; /* 0x04 */ 17 u32 int1; /* 0x08 */ 18 u8 res0[0x04]; /* 0x0c */ 19 u32 tcon0_frm_ctrl; /* 0x10 */ 20 u32 tcon0_frm_seed[6]; /* 0x14 */ 21 u32 tcon0_frm_table[4]; /* 0x2c */ 22 u8 res1[4]; /* 0x3c */ 23 u32 tcon0_ctrl; /* 0x40 */ 24 u32 tcon0_dclk; /* 0x44 */ 25 u32 tcon0_timing_active; /* 0x48 */ 26 u32 tcon0_timing_h; /* 0x4c */ 27 u32 tcon0_timing_v; /* 0x50 */ 28 u32 tcon0_timing_sync; /* 0x54 */ 29 u32 tcon0_hv_intf; /* 0x58 */ 30 u8 res2[0x04]; /* 0x5c */ 31 u32 tcon0_cpu_intf; /* 0x60 */ 32 u32 tcon0_cpu_wr_dat; /* 0x64 */ 33 u32 tcon0_cpu_rd_dat0; /* 0x68 */ 34 u32 tcon0_cpu_rd_dat1; /* 0x6c */ 35 u32 tcon0_ttl_timing0; /* 0x70 */ 36 u32 tcon0_ttl_timing1; /* 0x74 */ 37 u32 tcon0_ttl_timing2; /* 0x78 */ 38 u32 tcon0_ttl_timing3; /* 0x7c */ 39 u32 tcon0_ttl_timing4; /* 0x80 */ 40 u32 tcon0_lvds_intf; /* 0x84 */ 41 u32 tcon0_io_polarity; /* 0x88 */ 42 u32 tcon0_io_tristate; /* 0x8c */ 43 u32 tcon1_ctrl; /* 0x90 */ 44 u32 tcon1_timing_source; /* 0x94 */ 45 u32 tcon1_timing_scale; /* 0x98 */ 46 u32 tcon1_timing_out; /* 0x9c */ 47 u32 tcon1_timing_h; /* 0xa0 */ 48 u32 tcon1_timing_v; /* 0xa4 */ 49 u32 tcon1_timing_sync; /* 0xa8 */ 50 u8 res3[0x44]; /* 0xac */ 51 u32 tcon1_io_polarity; /* 0xf0 */ 52 u32 tcon1_io_tristate; /* 0xf4 */ 53 u8 res4[0x108]; /* 0xf8 */ 54 u32 mux_ctrl; /* 0x200 */ 55 u8 res5[0x1c]; /* 0x204 */ 56 u32 lvds_ana0; /* 0x220 */ 57 u32 lvds_ana1; /* 0x224 */ 58 }; 59 60 /* 61 * LCDC register constants. 62 */ 63 #define SUNXI_LCDC_X(x) (((x) - 1) << 16) 64 #define SUNXI_LCDC_Y(y) (((y) - 1) << 0) 65 #define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24) 66 #define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25) 67 #define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0) 68 #define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0) 69 #define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0) 70 #define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31) 71 #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4)) 72 #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4)) 73 #define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111 74 #define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000 75 #define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111 76 #define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555 77 #define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777 78 #define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) 79 #define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31) 80 #define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) 81 #define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28) 82 #define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) 83 #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) 84 #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) 85 #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) 86 #ifdef CONFIG_SUNXI_GEN_SUN6I 87 #define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20) 88 #else 89 #define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */ 90 #endif 91 #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) 92 #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) 93 #define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) 94 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) 95 #define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20) 96 #define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) 97 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) 98 #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) 99 #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) 100 #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16) 101 #define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0) 102 #define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0) 103 #define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4) 104 #define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4) 105 #ifdef CONFIG_SUNXI_GEN_SUN6I 106 #define SUNXI_LCDC_LVDS_ANA0 0x40040320 107 #define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) 108 #define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24) 109 #define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20) 110 #else 111 #define SUNXI_LCDC_LVDS_ANA0 0x3f310000 112 #define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) 113 #endif 114 #define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) 115 #define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) 116 117 void lcdc_init(struct sunxi_lcdc_reg * const lcdc); 118 void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth); 119 void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, 120 const struct display_timing *mode, 121 int clk_div, bool for_ext_vga_dac, 122 int depth, int dclk_phase); 123 void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc, 124 const struct display_timing *mode, 125 bool ext_hvsync, bool is_composite); 126 void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon, 127 int dotclock, int *clk_div, int *clk_double, 128 bool is_composite); 129 130 #endif /* _LCDC_H */ 131