1 /*
2  * Sunxi platform timing controller register and constant defines
3  *
4  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
5  * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef _LCDC_H
11 #define _LCDC_H
12 
13 #include <fdtdec.h>
14 
15 struct sunxi_lcdc_reg {
16 	u32 ctrl;			/* 0x00 */
17 	u32 int0;			/* 0x04 */
18 	u32 int1;			/* 0x08 */
19 	u8 res0[0x04];			/* 0x0c */
20 	u32 tcon0_frm_ctrl;		/* 0x10 */
21 	u32 tcon0_frm_seed[6];		/* 0x14 */
22 	u32 tcon0_frm_table[4];		/* 0x2c */
23 	u8 res1[4];			/* 0x3c */
24 	u32 tcon0_ctrl;			/* 0x40 */
25 	u32 tcon0_dclk;			/* 0x44 */
26 	u32 tcon0_timing_active;	/* 0x48 */
27 	u32 tcon0_timing_h;		/* 0x4c */
28 	u32 tcon0_timing_v;		/* 0x50 */
29 	u32 tcon0_timing_sync;		/* 0x54 */
30 	u32 tcon0_hv_intf;		/* 0x58 */
31 	u8 res2[0x04];			/* 0x5c */
32 	u32 tcon0_cpu_intf;		/* 0x60 */
33 	u32 tcon0_cpu_wr_dat;		/* 0x64 */
34 	u32 tcon0_cpu_rd_dat0;		/* 0x68 */
35 	u32 tcon0_cpu_rd_dat1;		/* 0x6c */
36 	u32 tcon0_ttl_timing0;		/* 0x70 */
37 	u32 tcon0_ttl_timing1;		/* 0x74 */
38 	u32 tcon0_ttl_timing2;		/* 0x78 */
39 	u32 tcon0_ttl_timing3;		/* 0x7c */
40 	u32 tcon0_ttl_timing4;		/* 0x80 */
41 	u32 tcon0_lvds_intf;		/* 0x84 */
42 	u32 tcon0_io_polarity;		/* 0x88 */
43 	u32 tcon0_io_tristate;		/* 0x8c */
44 	u32 tcon1_ctrl;			/* 0x90 */
45 	u32 tcon1_timing_source;	/* 0x94 */
46 	u32 tcon1_timing_scale;		/* 0x98 */
47 	u32 tcon1_timing_out;		/* 0x9c */
48 	u32 tcon1_timing_h;		/* 0xa0 */
49 	u32 tcon1_timing_v;		/* 0xa4 */
50 	u32 tcon1_timing_sync;		/* 0xa8 */
51 	u8 res3[0x44];			/* 0xac */
52 	u32 tcon1_io_polarity;		/* 0xf0 */
53 	u32 tcon1_io_tristate;		/* 0xf4 */
54 	u8 res4[0x108];			/* 0xf8 */
55 	u32 mux_ctrl;			/* 0x200 */
56 	u8 res5[0x1c];			/* 0x204 */
57 	u32 lvds_ana0;			/* 0x220 */
58 	u32 lvds_ana1;			/* 0x224 */
59 };
60 
61 /*
62  * LCDC register constants.
63  */
64 #define SUNXI_LCDC_X(x)				(((x) - 1) << 16)
65 #define SUNXI_LCDC_Y(y)				(((y) - 1) << 0)
66 #define SUNXI_LCDC_TCON_VSYNC_MASK		(1 << 24)
67 #define SUNXI_LCDC_TCON_HSYNC_MASK		(1 << 25)
68 #define SUNXI_LCDC_CTRL_IO_MAP_MASK		(1 << 0)
69 #define SUNXI_LCDC_CTRL_IO_MAP_TCON0		(0 << 0)
70 #define SUNXI_LCDC_CTRL_IO_MAP_TCON1		(1 << 0)
71 #define SUNXI_LCDC_CTRL_TCON_ENABLE		(1 << 31)
72 #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666	((1 << 31) | (0 << 4))
73 #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565	((1 << 31) | (5 << 4))
74 #define SUNXI_LCDC_TCON0_FRM_SEED		0x11111111
75 #define SUNXI_LCDC_TCON0_FRM_TAB0		0x01010000
76 #define SUNXI_LCDC_TCON0_FRM_TAB1		0x15151111
77 #define SUNXI_LCDC_TCON0_FRM_TAB2		0x57575555
78 #define SUNXI_LCDC_TCON0_FRM_TAB3		0x7f7f7777
79 #define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
80 #define SUNXI_LCDC_TCON0_CTRL_ENABLE		(1 << 31)
81 #define SUNXI_LCDC_TCON0_DCLK_DIV(n)		((n) << 0)
82 #define SUNXI_LCDC_TCON0_DCLK_ENABLE		(0xf << 28)
83 #define SUNXI_LCDC_TCON0_TIMING_H_BP(n)		(((n) - 1) << 0)
84 #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
85 #define SUNXI_LCDC_TCON0_TIMING_V_BP(n)		(((n) - 1) << 0)
86 #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n)	(((n) * 2) << 16)
87 #ifdef CONFIG_SUNXI_GEN_SUN6I
88 #define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0	(1 << 20)
89 #else
90 #define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0	0 /* NA */
91 #endif
92 #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n)	((n) << 26)
93 #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE	(1 << 31)
94 #define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x)	((x) << 28)
95 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
96 #define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE	(1 << 20)
97 #define SUNXI_LCDC_TCON1_CTRL_ENABLE		(1 << 31)
98 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n)		(((n) - 1) << 0)
99 #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
100 #define SUNXI_LCDC_TCON1_TIMING_V_BP(n)		(((n) - 1) << 0)
101 #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n)	((n) << 16)
102 #define SUNXI_LCDC_MUX_CTRL_SRC0_MASK		(0xf << 0)
103 #define SUNXI_LCDC_MUX_CTRL_SRC0(x)		((x) << 0)
104 #define SUNXI_LCDC_MUX_CTRL_SRC1_MASK		(0xf << 4)
105 #define SUNXI_LCDC_MUX_CTRL_SRC1(x)		((x) << 4)
106 #ifdef CONFIG_SUNXI_GEN_SUN6I
107 #define SUNXI_LCDC_LVDS_ANA0			0x40040320
108 #define SUNXI_LCDC_LVDS_ANA0_EN_MB		(1 << 31)
109 #define SUNXI_LCDC_LVDS_ANA0_DRVC		(1 << 24)
110 #define SUNXI_LCDC_LVDS_ANA0_DRVD(x)		((x) << 20)
111 #else
112 #define SUNXI_LCDC_LVDS_ANA0			0x3f310000
113 #define SUNXI_LCDC_LVDS_ANA0_UPDATE		(1 << 22)
114 #endif
115 #define SUNXI_LCDC_LVDS_ANA1_INIT1		(0x1f << 26 | 0x1f << 10)
116 #define SUNXI_LCDC_LVDS_ANA1_INIT2		(0x1f << 16 | 0x1f << 00)
117 
118 void lcdc_init(struct sunxi_lcdc_reg * const lcdc);
119 void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth);
120 void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
121 			 const struct display_timing *mode,
122 			 int clk_div, bool for_ext_vga_dac,
123 			 int depth, int dclk_phase);
124 void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
125 			 const struct display_timing *mode,
126 			 bool ext_hvsync, bool is_composite);
127 void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon,
128 		  int dotclock, int *clk_div, int *clk_double,
129 		  bool is_composite);
130 
131 #endif /* _LCDC_H */
132