1*ea1af9f2SPhilipp Tomsich /* 2*ea1af9f2SPhilipp Tomsich * GTBUS initialisation for sun9i 3*ea1af9f2SPhilipp Tomsich * 4*ea1af9f2SPhilipp Tomsich * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH 5*ea1af9f2SPhilipp Tomsich * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 6*ea1af9f2SPhilipp Tomsich * 7*ea1af9f2SPhilipp Tomsich * SPDX-License-Identifier: GPL-2.0+ 8*ea1af9f2SPhilipp Tomsich */ 9*ea1af9f2SPhilipp Tomsich 10*ea1af9f2SPhilipp Tomsich #ifndef _SUNXI_GTBUS_SUN9I_H 11*ea1af9f2SPhilipp Tomsich #define _SUNXI_GTBUS_SUN9I_H 12*ea1af9f2SPhilipp Tomsich 13*ea1af9f2SPhilipp Tomsich #include <linux/types.h> 14*ea1af9f2SPhilipp Tomsich 15*ea1af9f2SPhilipp Tomsich struct sunxi_gtbus_reg { 16*ea1af9f2SPhilipp Tomsich u32 mst_cfg[36]; /* 0x000 */ 17*ea1af9f2SPhilipp Tomsich u8 reserved1[0x70]; /* 0x090 */ 18*ea1af9f2SPhilipp Tomsich u32 bw_wdw_cfg; /* 0x100 */ 19*ea1af9f2SPhilipp Tomsich u32 mst_read_prio_cfg[2]; /* 0x104 */ 20*ea1af9f2SPhilipp Tomsich u32 lvl2_mst_cfg; /* 0x10c */ 21*ea1af9f2SPhilipp Tomsich u32 sw_clk_on; /* 0x110 */ 22*ea1af9f2SPhilipp Tomsich u32 sw_clk_off; /* 0x114 */ 23*ea1af9f2SPhilipp Tomsich u32 pmu_mst_en; /* 0x118 */ 24*ea1af9f2SPhilipp Tomsich u32 pmu_cfg; /* 0x11c */ 25*ea1af9f2SPhilipp Tomsich u32 pmu_cnt[19]; /* 0x120 */ 26*ea1af9f2SPhilipp Tomsich u32 reserved2[0x94]; /* 0x16c */ 27*ea1af9f2SPhilipp Tomsich u32 cci400_config[3]; /* 0x200 */ 28*ea1af9f2SPhilipp Tomsich u32 cci400_status[2]; /* 0x20c */ 29*ea1af9f2SPhilipp Tomsich }; 30*ea1af9f2SPhilipp Tomsich 31*ea1af9f2SPhilipp Tomsich /* for register GT_MST_CFG_REG(n) */ 32*ea1af9f2SPhilipp Tomsich #define GT_ENABLE_REQ (1<<31) /* clock on */ 33*ea1af9f2SPhilipp Tomsich #define GT_DISABLE_REQ (1<<30) /* clock off */ 34*ea1af9f2SPhilipp Tomsich #define GT_QOS_SHIFT 28 35*ea1af9f2SPhilipp Tomsich #define GT_THD1_SHIFT 16 36*ea1af9f2SPhilipp Tomsich #define GT_REQN_MAX 0xf /* max no master requests in one cycle */ 37*ea1af9f2SPhilipp Tomsich #define GT_REQN_SHIFT 12 38*ea1af9f2SPhilipp Tomsich #define GT_THD0_SHIFT 0 39*ea1af9f2SPhilipp Tomsich 40*ea1af9f2SPhilipp Tomsich #define GT_QOS_MAX 0x3 41*ea1af9f2SPhilipp Tomsich #define GT_THD_MAX 0xfff 42*ea1af9f2SPhilipp Tomsich #define GT_BW_WDW_MAX 0xffff 43*ea1af9f2SPhilipp Tomsich 44*ea1af9f2SPhilipp Tomsich /* mst_read_prio_cfg */ 45*ea1af9f2SPhilipp Tomsich #define GT_PRIO_LOW 0 46*ea1af9f2SPhilipp Tomsich #define GT_PRIO_HIGH 1 47*ea1af9f2SPhilipp Tomsich 48*ea1af9f2SPhilipp Tomsich /* GTBUS port ids */ 49*ea1af9f2SPhilipp Tomsich #define GT_PORT_CPUM1 0 50*ea1af9f2SPhilipp Tomsich #define GT_PORT_CPUM2 1 51*ea1af9f2SPhilipp Tomsich #define GT_PORT_SATA 2 52*ea1af9f2SPhilipp Tomsich #define GT_PORT_USB3 3 53*ea1af9f2SPhilipp Tomsich #define GT_PORT_FE0 4 54*ea1af9f2SPhilipp Tomsich #define GT_PORT_BE1 5 55*ea1af9f2SPhilipp Tomsich #define GT_PORT_BE2 6 56*ea1af9f2SPhilipp Tomsich #define GT_PORT_IEP0 7 57*ea1af9f2SPhilipp Tomsich #define GT_PORT_FE1 8 58*ea1af9f2SPhilipp Tomsich #define GT_PORT_BE0 9 59*ea1af9f2SPhilipp Tomsich #define GT_PORT_FE2 10 60*ea1af9f2SPhilipp Tomsich #define GT_PORT_IEP1 11 61*ea1af9f2SPhilipp Tomsich #define GT_PORT_VED 12 62*ea1af9f2SPhilipp Tomsich #define GT_PORT_VEE 13 63*ea1af9f2SPhilipp Tomsich #define GT_PORT_FD 14 64*ea1af9f2SPhilipp Tomsich #define GT_PORT_CSI 15 65*ea1af9f2SPhilipp Tomsich #define GT_PORT_MP 16 66*ea1af9f2SPhilipp Tomsich #define GT_PORT_HSI 17 67*ea1af9f2SPhilipp Tomsich #define GT_PORT_SS 18 68*ea1af9f2SPhilipp Tomsich #define GT_PORT_TS 19 69*ea1af9f2SPhilipp Tomsich #define GT_PORT_DMA 20 70*ea1af9f2SPhilipp Tomsich #define GT_PORT_NDFC0 21 71*ea1af9f2SPhilipp Tomsich #define GT_PORT_NDFC1 22 72*ea1af9f2SPhilipp Tomsich #define GT_PORT_CPUS 23 73*ea1af9f2SPhilipp Tomsich #define GT_PORT_TH 24 74*ea1af9f2SPhilipp Tomsich #define GT_PORT_GMAC 25 75*ea1af9f2SPhilipp Tomsich #define GT_PORT_USB0 26 76*ea1af9f2SPhilipp Tomsich #define GT_PORT_MSTG0 27 77*ea1af9f2SPhilipp Tomsich #define GT_PORT_MSTG1 28 78*ea1af9f2SPhilipp Tomsich #define GT_PORT_MSTG2 29 79*ea1af9f2SPhilipp Tomsich #define GT_PORT_MSTG3 30 80*ea1af9f2SPhilipp Tomsich #define GT_PORT_USB1 31 81*ea1af9f2SPhilipp Tomsich #define GT_PORT_GPU0 32 82*ea1af9f2SPhilipp Tomsich #define GT_PORT_GPU1 33 83*ea1af9f2SPhilipp Tomsich #define GT_PORT_USB2 34 84*ea1af9f2SPhilipp Tomsich #define GT_PORT_CPUM0 35 85*ea1af9f2SPhilipp Tomsich 86*ea1af9f2SPhilipp Tomsich #define GP_MST_CFG_DEFAULT \ 87*ea1af9f2SPhilipp Tomsich ((GT_QOS_MAX << GT_QOS_SHIFT) | \ 88*ea1af9f2SPhilipp Tomsich (GT_THD_MAX << GT_THD1_SHIFT) | \ 89*ea1af9f2SPhilipp Tomsich (GT_REQN_MAX << GT_REQN_SHIFT) | \ 90*ea1af9f2SPhilipp Tomsich (GT_THD_MAX << GT_THD0_SHIFT)) 91*ea1af9f2SPhilipp Tomsich 92*ea1af9f2SPhilipp Tomsich #endif 93