1 /*
2  * H6 dram controller register and constant defines
3  *
4  * (C) Copyright 2017  Icenowy Zheng <icenowy@aosc.io>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef _SUNXI_DRAM_SUN50I_H6_H
10 #define _SUNXI_DRAM_SUN50I_H6_H
11 
12 enum sunxi_dram_type {
13 	SUNXI_DRAM_TYPE_DDR3 = 3,
14 	SUNXI_DRAM_TYPE_DDR4,
15 	SUNXI_DRAM_TYPE_LPDDR2 = 6,
16 	SUNXI_DRAM_TYPE_LPDDR3,
17 };
18 
19 /*
20  * The following information is mainly retrieved by disassembly and some FPGA
21  * test code of sun50iw3 platform.
22  */
23 struct sunxi_mctl_com_reg {
24 	u32 cr;			/* 0x000 control register */
25 	u8 reserved_0x004[4];	/* 0x004 */
26 	u32 unk_0x008;		/* 0x008 */
27 	u32 tmr;		/* 0x00c timer register */
28 	u8 reserved_0x010[4];	/* 0x010 */
29 	u32 unk_0x014;		/* 0x014 */
30 	u8 reserved_0x018[8];	/* 0x018 */
31 	u32 maer0;		/* 0x020 master enable register 0 */
32 	u32 maer1;		/* 0x024 master enable register 1 */
33 	u32 maer2;		/* 0x028 master enable register 2 */
34 	u8 reserved_0x02c[468];	/* 0x02c */
35 	u32 bwcr;		/* 0x200 bandwidth control register */
36 	u8 reserved_0x204[12];	/* 0x204 */
37 	/*
38 	 * The last master configured by BSP libdram is at 0x49x, so the
39 	 * size of this struct array is set to 41 (0x29) now.
40 	 */
41 	struct {
42 		u32 cfg0;		/* 0x0 */
43 		u32 cfg1;		/* 0x4 */
44 		u8 reserved_0x8[8];	/* 0x8 */
45 	} master[41];		/* 0x210 + index * 0x10 */
46 };
47 check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498);
48 
49 /*
50  * The following register information are retrieved from some similar DRAM
51  * controllers, including the DRAM controllers in Allwinner A23/A80 SoCs,
52  * Rockchip RK3328 SoC, NXP i.MX7 SoCs and Xilinx Zynq UltraScale+ SoCs.
53  *
54  * The DRAM controller in Allwinner A23/A80 SoCs and NXP i.MX7 SoCs seems
55  * to be older than the one in Allwinner H6, as the DRAMTMG9 register
56  * is missing in these SoCs. (From the product specifications of these
57  * SoCs they're not capable of DDR4)
58  *
59  * Information sources:
60  * - dram_sun9i.h and dram_sun8i_a23.h in the same directory.
61  * - sdram_rk3328.h from the RK3328 TPL DRAM patchset
62  * - i.MX 7Solo Applications Processor Reference Manual (IMX7SRM)
63  * - Zynq UltraScale+ MPSoC Register Reference (UG1087)
64  */
65 struct sunxi_mctl_ctl_reg {
66 	u32 mstr;		/* 0x000 */
67 	u32 statr;		/* 0x004 unused */
68 	u32 mstr1;		/* 0x008 unused */
69 	u32 unk_0x00c;		/* 0x00c */
70 	u32 mrctrl0;		/* 0x010 unused */
71 	u32 mrctrl1;		/* 0x014 unused */
72 	u32 mrstatr;		/* 0x018 unused */
73 	u32 mrctrl2;		/* 0x01c unused */
74 	u32 derateen;		/* 0x020 unused */
75 	u32 derateint;		/* 0x024 unused */
76 	u8 reserved_0x028[8];	/* 0x028 */
77 	u32 pwrctl;		/* 0x030 unused */
78 	u32 pwrtmg;		/* 0x034 unused */
79 	u32 hwlpctl;		/* 0x038 unused */
80 	u8 reserved_0x03c[20];	/* 0x03c */
81 	u32 rfshctl0;		/* 0x050 unused */
82 	u32 rfshctl1;		/* 0x054 unused */
83 	u8 reserved_0x058[8];	/* 0x05c */
84 	u32 rfshctl3;		/* 0x060 */
85 	u32 rfshtmg;		/* 0x064 */
86 	u8 reserved_0x068[104];	/* 0x068 reserved for ECC&CRC (from ZynqMP) */
87 	u32 init[8];		/* 0x0d0 */
88 	u32 dimmctl;		/* 0x0f0 unused */
89 	u32 rankctl;		/* 0x0f4 */
90 	u8 reserved_0x0f8[8];	/* 0x0f8 */
91 	u32 dramtmg[17];	/* 0x100 */
92 	u8 reserved_0x144[60];	/* 0x144 */
93 	u32 zqctl[3];		/* 0x180 */
94 	u32 zqstat;		/* 0x18c unused */
95 	u32 dfitmg0;		/* 0x190 */
96 	u32 dfitmg1;		/* 0x194 */
97 	u32 dfilpcfg[2];	/* 0x198 unused */
98 	u32 dfiupd[3];		/* 0x1a0 */
99 	u32 reserved_0x1ac;	/* 0x1ac */
100 	u32 dfimisc;		/* 0x1b0 */
101 	u32 dfitmg2;		/* 0x1b4 unused, may not exist */
102 	u8 reserved_0x1b8[8];	/* 0x1b8 */
103 	u32 dbictl;		/* 0x1c0 */
104 	u8 reserved_0x1c4[60];	/* 0x1c4 */
105 	u32 addrmap[12];	/* 0x200 */
106 	u8 reserved_0x230[16];	/* 0x230 */
107 	u32 odtcfg;		/* 0x240 */
108 	u32 odtmap;		/* 0x244 */
109 	u8 reserved_0x248[8];	/* 0x248 */
110 	u32 sched[2];		/* 0x250 */
111 	u8 reserved_0x258[180];	/* 0x258 */
112 	u32 dbgcmd;		/* 0x30c unused */
113 	u32 dbgstat;		/* 0x310 unused */
114 	u8 reserved_0x314[12];	/* 0x314 */
115 	u32 swctl;		/* 0x320 */
116 	u32 swstat;		/* 0x324 */
117 };
118 check_member(sunxi_mctl_ctl_reg, swstat, 0x324);
119 
120 #define MSTR_DEVICETYPE_DDR3	BIT(0)
121 #define MSTR_DEVICETYPE_LPDDR2	BIT(2)
122 #define MSTR_DEVICETYPE_LPDDR3	BIT(3)
123 #define MSTR_DEVICETYPE_DDR4	BIT(4)
124 #define MSTR_DEVICETYPE_MASK	GENMASK(5, 0)
125 #define MSTR_2TMODE		BIT(10)
126 #define MSTR_BUSWIDTH_FULL	(0 << 12)
127 #define MSTR_BUSWIDTH_HALF	(1 << 12)
128 #define MSTR_ACTIVE_RANKS(x)	(((x == 2) ? 3 : 1) << 24)
129 #define MSTR_BURST_LENGTH(x)	(((x) >> 1) << 16)
130 
131 /*
132  * The following register information is based on Zynq UltraScale+
133  * MPSoC Register Reference, as it's the currently only known
134  * DDR PHY similar to the one used in H6; however although the
135  * map is similar, the bit fields definitions are different.
136  *
137  * Other DesignWare DDR PHY's have similar register names, but the
138  * offset and definitions are both different.
139  */
140 struct sunxi_mctl_phy_reg {
141 	u32 ver;		/* 0x000 guess based on similar PHYs */
142 	u32 pir;		/* 0x004 */
143 	u8 reserved_0x008[8];	/* 0x008 */
144 	/*
145 	 * The ZynqMP manual didn't document PGCR1, however this register
146 	 * exists on H6 and referenced by libdram.
147 	 */
148 	u32 pgcr[8];		/* 0x010 */
149 	/*
150 	 * By comparing the hardware and the ZynqMP manual, the PGSR seems
151 	 * to start at 0x34 on H6.
152 	 */
153 	u8 reserved_0x030[4];	/* 0x030 */
154 	u32 pgsr[3];		/* 0x034 */
155 	u32 ptr[7];		/* 0x040 */
156 	/*
157 	 * According to ZynqMP reference there's PLLCR0~6 in this area,
158 	 * but they're tagged "Type B PLL Only" and H6 seems to have
159 	 * no them.
160 	 * 0x080 is not present in ZynqMP reference but it seems to be
161 	 * present on H6.
162 	 */
163 	u8 reserved_0x05c[36];	/* 0x05c */
164 	u32 unk_0x080;		/* 0x080 */
165 	u8 reserved_0x084[4];	/* 0x084 */
166 	u32 dxccr;		/* 0x088 */
167 	u8 reserved_0x08c[4];	/* 0x08c */
168 	u32 dsgcr;		/* 0x090 */
169 	u8 reserved_0x094[4];	/* 0x094 */
170 	u32 odtcr;		/* 0x098 */
171 	u8 reserved_0x09c[4];	/* 0x09c */
172 	u32 aacr;		/* 0x0a0 */
173 	u8 reserved_0x0a4[32];	/* 0x0a4 */
174 	u32 gpr1;		/* 0x0c4 */
175 	u8 reserved_0x0c8[56];	/* 0x0c8 */
176 	u32 dcr;		/* 0x100 */
177 	u8 reserved_0x104[12];	/* 0x104 */
178 	u32 dtpr[7];		/* 0x110 */
179 	u8 reserved_0x12c[20];	/* 0x12c */
180 	u32 rdimmgcr[3];	/* 0x140 */
181 	u8 reserved_0x14c[4];	/* 0x14c */
182 	u32 rdimmcr[5];		/* 0x150 */
183 	u8 reserved_0x164[4];	/* 0x164 */
184 	u32 schcr[2];		/* 0x168 */
185 	u8 reserved_0x170[16];	/* 0x170 */
186 	/*
187 	 * The ZynqMP manual documents MR0~7, 11~14 and 22.
188 	 */
189 	u32 mr[23];		/* 0x180 */
190 	u8 reserved_0x1dc[36];	/* 0x1dc */
191 	u32 dtcr[2];		/* 0x200 */
192 	u32 dtar[3];		/* 0x208 */
193 	u8 reserved_0x214[4];	/* 0x214 */
194 	u32 dtdr[2];		/* 0x218 */
195 	u8 reserved_0x220[16];	/* 0x220 */
196 	u32 dtedr0;		/* 0x230 */
197 	u32 dtedr1;		/* 0x234 */
198 	u32 dtedr2;		/* 0x238 */
199 	u32 vtdr;		/* 0x23c */
200 	u32 catr[2];		/* 0x240 */
201 	u8 reserved_0x248[8];
202 	u32 dqsdr[3];		/* 0x250 */
203 	u32 dtedr3;		/* 0x25c */
204 	u8 reserved_0x260[160];	/* 0x260 */
205 	u32 dcuar;		/* 0x300 */
206 	u32 dcudr;		/* 0x304 */
207 	u32 dcurr;		/* 0x308 */
208 	u32 dculr;		/* 0x30c */
209 	u32 dcugcr;		/* 0x310 */
210 	u32 dcutpr;		/* 0x314 */
211 	u32 dcusr[2];		/* 0x318 */
212 	u8 reserved_0x320[444];	/* 0x320 */
213 	u32 rankidr;		/* 0x4dc */
214 	u32 riocr[6];		/* 0x4e0 */
215 	u8 reserved_0x4f8[8];	/* 0x4f8 */
216 	u32 aciocr[6];		/* 0x500 */
217 	u8 reserved_0x518[8];	/* 0x518 */
218 	u32 iovcr[2];		/* 0x520 */
219 	u32 vtcr[2];		/* 0x528 */
220 	u8 reserved_0x530[16];	/* 0x530 */
221 	u32 acbdlr[17];		/* 0x540 */
222 	u32 aclcdlr;		/* 0x584 */
223 	u8 reserved_0x588[24];	/* 0x588 */
224 	u32 acmdlr[2];		/* 0x5a0 */
225 	u8 reserved_0x5a8[216];	/* 0x5a8 */
226 	struct {
227 		u32 zqcr;	/* 0x00 only the first one valid */
228 		u32 zqpr[2];	/* 0x04 */
229 		u32 zqdr[2];	/* 0x0c */
230 		u32 zqor[2];	/* 0x14 */
231 		u32 zqsr;	/* 0x1c */
232 	} zq[2];		/* 0x680, 0x6a0 */
233 	u8 reserved_0x6c0[64];	/* 0x6c0 */
234 	struct {
235 		u32 gcr[7];		/* 0x00 */
236 		u8 reserved_0x1c[36];	/* 0x1c */
237 		u32 bdlr0;		/* 0x40 */
238 		u32 bdlr1;		/* 0x44 */
239 		u32 bdlr2;		/* 0x48 */
240 		u8 reserved_0x4c[4];	/* 0x4c */
241 		u32 bdlr3;		/* 0x50 */
242 		u32 bdlr4;		/* 0x54 */
243 		u32 bdlr5;		/* 0x58 */
244 		u8 reserved_0x5c[4];	/* 0x5c */
245 		u32 bdlr6;		/* 0x60 */
246 		u8 reserved_0x64[28];	/* 0x64 */
247 		u32 lcdlr[6];		/* 0x80 */
248 		u8 reserved_0x98[8];	/* 0x98 */
249 		u32 mdlr[2];		/* 0xa0 */
250 		u8 reserved_0xa8[24];	/* 0xa8 */
251 		u32 gtr0;		/* 0xc0 */
252 		u8 reserved_0xc4[12];	/* 0xc4 */
253 		/*
254 		 * DXnRSR0 is not documented in ZynqMP manual but
255 		 * it's used in libdram.
256 		 */
257 		u32 rsr[4];		/* 0xd0 */
258 		u32 gsr[4];		/* 0xe0 */
259 		u8 reserved_0xf0[16];	/* 0xf0 */
260 	} dx[4];		/* 0x700, 0x800, 0x900, 0xa00 */
261 };
262 check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0);
263 
264 #define PIR_INIT	BIT(0)
265 #define PIR_ZCAL	BIT(1)
266 #define PIR_CA		BIT(2)
267 #define PIR_PLLINIT	BIT(4)
268 #define PIR_DCAL	BIT(5)
269 #define PIR_PHYRST	BIT(6)
270 #define PIR_DRAMRST	BIT(7)
271 #define PIR_DRAMINIT	BIT(8)
272 #define PIR_WL		BIT(9)
273 #define PIR_QSGATE	BIT(10)
274 #define PIR_WLADJ	BIT(11)
275 #define PIR_RDDSKW	BIT(12)
276 #define PIR_WRDSKW	BIT(13)
277 #define PIR_RDEYE	BIT(14)
278 #define PIR_WREYE	BIT(15)
279 #define PIR_VREF	BIT(17)
280 #define PIR_CTLDINIT	BIT(18)
281 #define PIR_DQS2DQ	BIT(20)
282 #define PIR_DCALPSE	BIT(29)
283 #define PIR_ZCALBYP	BIT(30)
284 
285 #define DCR_LPDDR3	(1 << 0)
286 #define DCR_DDR3	(3 << 0)
287 #define DCR_DDR4	(4 << 0)
288 #define DCR_DDR8BANK	BIT(3)
289 
290 static inline int ns_to_t(int nanoseconds)
291 {
292 	const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
293 
294 	return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
295 }
296 
297 #endif /* _SUNXI_DRAM_SUN50I_H6_H */
298