1 /*
2  * (C) Copyright 2007-2012
3  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4  * Berg Xing <bergxing@allwinnertech.com>
5  * Tom Cubie <tangliang@allwinnertech.com>
6  *
7  * Sunxi platform dram register definition.
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #ifndef _SUNXI_DRAM_SUN4I_H
13 #define _SUNXI_DRAM_SUN4I_H
14 
15 struct sunxi_dram_reg {
16 	u32 ccr;		/* 0x00 controller configuration register */
17 	u32 dcr;		/* 0x04 dram configuration register */
18 	u32 iocr;		/* 0x08 i/o configuration register */
19 	u32 csr;		/* 0x0c controller status register */
20 	u32 drr;		/* 0x10 dram refresh register */
21 	u32 tpr0;		/* 0x14 dram timing parameters register 0 */
22 	u32 tpr1;		/* 0x18 dram timing parameters register 1 */
23 	u32 tpr2;		/* 0x1c dram timing parameters register 2 */
24 	u32 gdllcr;		/* 0x20 global dll control register */
25 	u8 res0[0x28];
26 	u32 rslr0;		/* 0x4c rank system latency register */
27 	u32 rslr1;		/* 0x50 rank system latency register */
28 	u8 res1[0x8];
29 	u32 rdgr0;		/* 0x5c rank dqs gating register */
30 	u32 rdgr1;		/* 0x60 rank dqs gating register */
31 	u8 res2[0x34];
32 	u32 odtcr;		/* 0x98 odt configuration register */
33 	u32 dtr0;		/* 0x9c data training register 0 */
34 	u32 dtr1;		/* 0xa0 data training register 1 */
35 	u32 dtar;		/* 0xa4 data training address register */
36 	u32 zqcr0;		/* 0xa8 zq control register 0 */
37 	u32 zqcr1;		/* 0xac zq control register 1 */
38 	u32 zqsr;		/* 0xb0 zq status register */
39 	u32 idcr;		/* 0xb4 initializaton delay configure reg */
40 	u8 res3[0x138];
41 	u32 mr;			/* 0x1f0 mode register */
42 	u32 emr;		/* 0x1f4 extended mode register */
43 	u32 emr2;		/* 0x1f8 extended mode register */
44 	u32 emr3;		/* 0x1fc extended mode register */
45 	u32 dllctr;		/* 0x200 dll control register */
46 	u32 dllcr[5];		/* 0x204 dll control register 0(byte 0) */
47 	/* 0x208 dll control register 1(byte 1) */
48 	/* 0x20c dll control register 2(byte 2) */
49 	/* 0x210 dll control register 3(byte 3) */
50 	/* 0x214 dll control register 4(byte 4) */
51 	u32 dqtr0;		/* 0x218 dq timing register */
52 	u32 dqtr1;		/* 0x21c dq timing register */
53 	u32 dqtr2;		/* 0x220 dq timing register */
54 	u32 dqtr3;		/* 0x224 dq timing register */
55 	u32 dqstr;		/* 0x228 dqs timing register */
56 	u32 dqsbtr;		/* 0x22c dqsb timing register */
57 	u32 mcr;		/* 0x230 mode configure register */
58 	u8 res[0x8];
59 	u32 ppwrsctl;		/* 0x23c pad power save control */
60 	u32 apr;		/* 0x240 arbiter period register */
61 	u32 pldtr;		/* 0x244 priority level data threshold reg */
62 	u8 res5[0x8];
63 	u32 hpcr[32];		/* 0x250 host port configure register */
64 	u8 res6[0x10];
65 	u32 csel;		/* 0x2e0 controller select register */
66 };
67 
68 struct dram_para {
69 	u32 clock;
70 	u32 mbus_clock;
71 	u32 type;
72 	u32 rank_num;
73 	u32 density;
74 	u32 io_width;
75 	u32 bus_width;
76 	u32 cas;
77 	u32 zq;
78 	u32 odt_en;
79 	u32 size;
80 	u32 tpr0;
81 	u32 tpr1;
82 	u32 tpr2;
83 	u32 tpr3;
84 	u32 tpr4;
85 	u32 tpr5;
86 	u32 emr1;
87 	u32 emr2;
88 	u32 emr3;
89 	u32 dqs_gating_delay;
90 	u32 active_windowing;
91 };
92 
93 #define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5)
94 #define DRAM_CCR_DQS_GATE (0x1 << 14)
95 #define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17)
96 #define DRAM_CCR_ITM_OFF (0x1 << 28)
97 #define DRAM_CCR_DATA_TRAINING (0x1 << 30)
98 #define DRAM_CCR_INIT (0x1 << 31)
99 
100 #define DRAM_MEMORY_TYPE_DDR1 1
101 #define DRAM_MEMORY_TYPE_DDR2 2
102 #define DRAM_MEMORY_TYPE_DDR3 3
103 #define DRAM_MEMORY_TYPE_LPDDR2 4
104 #define DRAM_MEMORY_TYPE_LPDDR 5
105 #define DRAM_DCR_TYPE (0x1 << 0)
106 #define DRAM_DCR_TYPE_DDR2 0x0
107 #define DRAM_DCR_TYPE_DDR3 0x1
108 #define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1)
109 #define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3)
110 #define DRAM_DCR_IO_WIDTH_8BIT 0x0
111 #define DRAM_DCR_IO_WIDTH_16BIT 0x1
112 #define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3)
113 #define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7)
114 #define DRAM_DCR_CHIP_DENSITY_256M 0x0
115 #define DRAM_DCR_CHIP_DENSITY_512M 0x1
116 #define DRAM_DCR_CHIP_DENSITY_1024M 0x2
117 #define DRAM_DCR_CHIP_DENSITY_2048M 0x3
118 #define DRAM_DCR_CHIP_DENSITY_4096M 0x4
119 #define DRAM_DCR_CHIP_DENSITY_8192M 0x5
120 #define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6)
121 #define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7)
122 #define DRAM_DCR_BUS_WIDTH_32BIT 0x3
123 #define DRAM_DCR_BUS_WIDTH_16BIT 0x1
124 #define DRAM_DCR_BUS_WIDTH_8BIT 0x0
125 #define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
126 #define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
127 #define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)
128 #define DRAM_DCR_MODE(n) (((n) & 0x3) << 13)
129 #define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3)
130 #define DRAM_DCR_MODE_SEQ 0x0
131 #define DRAM_DCR_MODE_INTERLEAVE 0x1
132 
133 #define DRAM_CSR_DTERR  (0x1 << 20)
134 #define DRAM_CSR_DTIERR (0x1 << 21)
135 #define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR)
136 
137 #define DRAM_DRR_TRFC(n) ((n) & 0xff)
138 #define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)
139 #define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24)
140 
141 #define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0)
142 #define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3)
143 #define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2)
144 #define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3)
145 #define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4)
146 #define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3)
147 #define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6)
148 #define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3)
149 #define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8)
150 #define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7)
151 #define DRAM_MCR_MODE_ADDR_IN (0x1 << 11)
152 #define DRAM_MCR_RESET (0x1 << 12)
153 #define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13)
154 #define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3)
155 #define DRAM_MCR_DCLK_OUT (0x1 << 16)
156 
157 #define DRAM_DLLCR_NRESET (0x1 << 30)
158 #define DRAM_DLLCR_DISABLE (0x1 << 31)
159 
160 #define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20)
161 #define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
162 #define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */
163 #define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */
164 
165 #define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */
166 
167 #define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0)
168 #define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3)
169 
170 #define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0)
171 #define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7)
172 #define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4)
173 #define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7)
174 #define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9)
175 #define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7)
176 #define DRAM_MR_POWER_DOWN (0x1 << 12)
177 
178 #define DRAM_CSEL_MAGIC 0x16237495
179 
180 unsigned long dramc_init(struct dram_para *para);
181 
182 #endif /* _SUNXI_DRAM_SUN4I_H */
183