1 /* 2 * Sunxi platform display controller register and constant defines 3 * 4 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> 5 * 6 * Based on out of tree Linux DRM driver defines: 7 * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr> 8 * Copyright (c) 2016 Allwinnertech Co., Ltd. 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef _SUNXI_DISPLAY2_H 14 #define _SUNXI_DISPLAY2_H 15 16 /* internal clock settings */ 17 struct de_clk { 18 u32 gate_cfg; 19 u32 bus_cfg; 20 u32 rst_cfg; 21 u32 div_cfg; 22 u32 sel_cfg; 23 }; 24 25 /* global control */ 26 struct de_glb { 27 u32 ctl; 28 u32 status; 29 u32 dbuff; 30 u32 size; 31 }; 32 33 /* alpha blending */ 34 struct de_bld { 35 u32 fcolor_ctl; 36 struct { 37 u32 fcolor; 38 u32 insize; 39 u32 offset; 40 u32 dum; 41 } attr[4]; 42 u32 dum0[15]; 43 u32 route; 44 u32 premultiply; 45 u32 bkcolor; 46 u32 output_size; 47 u32 bld_mode[4]; 48 u32 dum1[4]; 49 u32 ck_ctl; 50 u32 ck_cfg; 51 u32 dum2[2]; 52 u32 ck_max[4]; 53 u32 dum3[4]; 54 u32 ck_min[4]; 55 u32 dum4[3]; 56 u32 out_ctl; 57 }; 58 59 /* VI channel */ 60 struct de_vi { 61 struct { 62 u32 attr; 63 u32 size; 64 u32 coord; 65 u32 pitch[3]; 66 u32 top_laddr[3]; 67 u32 bot_laddr[3]; 68 } cfg[4]; 69 u32 fcolor[4]; 70 u32 top_haddr[3]; 71 u32 bot_haddr[3]; 72 u32 ovl_size[2]; 73 u32 hori[2]; 74 u32 vert[2]; 75 }; 76 77 struct de_ui { 78 struct { 79 u32 attr; 80 u32 size; 81 u32 coord; 82 u32 pitch; 83 u32 top_laddr; 84 u32 bot_laddr; 85 u32 fcolor; 86 u32 dum; 87 } cfg[4]; 88 u32 top_haddr; 89 u32 bot_haddr; 90 u32 ovl_size; 91 }; 92 93 struct de_csc { 94 u32 csc_ctl; 95 u8 res[0xc]; 96 u32 coef11; 97 u32 coef12; 98 u32 coef13; 99 u32 coef14; 100 u32 coef21; 101 u32 coef22; 102 u32 coef23; 103 u32 coef24; 104 u32 coef31; 105 u32 coef32; 106 u32 coef33; 107 u32 coef34; 108 }; 109 110 /* 111 * DE register constants. 112 */ 113 #define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000) 114 #define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000) 115 116 #define SUNXI_DE2_MUX_GLB_REGS 0x00000 117 #define SUNXI_DE2_MUX_BLD_REGS 0x01000 118 #define SUNXI_DE2_MUX_CHAN_REGS 0x02000 119 #define SUNXI_DE2_MUX_CHAN_SZ 0x1000 120 #define SUNXI_DE2_MUX_VSU_REGS 0x20000 121 #define SUNXI_DE2_MUX_GSU1_REGS 0x30000 122 #define SUNXI_DE2_MUX_GSU2_REGS 0x40000 123 #define SUNXI_DE2_MUX_GSU3_REGS 0x50000 124 #define SUNXI_DE2_MUX_FCE_REGS 0xa0000 125 #define SUNXI_DE2_MUX_BWS_REGS 0xa2000 126 #define SUNXI_DE2_MUX_LTI_REGS 0xa4000 127 #define SUNXI_DE2_MUX_PEAK_REGS 0xa6000 128 #define SUNXI_DE2_MUX_ASE_REGS 0xa8000 129 #define SUNXI_DE2_MUX_FCC_REGS 0xaa000 130 #define SUNXI_DE2_MUX_DCSC_REGS 0xb0000 131 132 #define SUNXI_DE2_FORMAT_XRGB_8888 4 133 #define SUNXI_DE2_FORMAT_RGB_565 10 134 135 #define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0) 136 #define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0) 137 #define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8) 138 139 #define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1)) 140 141 #endif /* _SUNXI_DISPLAY2_H */ 142