1 /* 2 * Sunxi platform display controller register and constant defines 3 * 4 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _SUNXI_DISPLAY_H 10 #define _SUNXI_DISPLAY_H 11 12 struct sunxi_de_fe_reg { 13 u32 enable; /* 0x000 */ 14 u32 frame_ctrl; /* 0x004 */ 15 u32 bypass; /* 0x008 */ 16 u32 algorithm_sel; /* 0x00c */ 17 u32 line_int_ctrl; /* 0x010 */ 18 u8 res0[0x0c]; /* 0x014 */ 19 u32 ch0_addr; /* 0x020 */ 20 u32 ch1_addr; /* 0x024 */ 21 u32 ch2_addr; /* 0x028 */ 22 u32 field_sequence; /* 0x02c */ 23 u32 ch0_offset; /* 0x030 */ 24 u32 ch1_offset; /* 0x034 */ 25 u32 ch2_offset; /* 0x038 */ 26 u8 res1[0x04]; /* 0x03c */ 27 u32 ch0_stride; /* 0x040 */ 28 u32 ch1_stride; /* 0x044 */ 29 u32 ch2_stride; /* 0x048 */ 30 u32 input_fmt; /* 0x04c */ 31 u32 ch3_addr; /* 0x050 */ 32 u32 ch4_addr; /* 0x054 */ 33 u32 ch5_addr; /* 0x058 */ 34 u32 output_fmt; /* 0x05c */ 35 u32 int_enable; /* 0x060 */ 36 u32 int_status; /* 0x064 */ 37 u32 status; /* 0x068 */ 38 u8 res2[0x04]; /* 0x06c */ 39 u32 csc_coef00; /* 0x070 */ 40 u32 csc_coef01; /* 0x074 */ 41 u32 csc_coef02; /* 0x078 */ 42 u32 csc_coef03; /* 0x07c */ 43 u32 csc_coef10; /* 0x080 */ 44 u32 csc_coef11; /* 0x084 */ 45 u32 csc_coef12; /* 0x088 */ 46 u32 csc_coef13; /* 0x08c */ 47 u32 csc_coef20; /* 0x090 */ 48 u32 csc_coef21; /* 0x094 */ 49 u32 csc_coef22; /* 0x098 */ 50 u32 csc_coef23; /* 0x09c */ 51 u32 deinterlace_ctrl; /* 0x0a0 */ 52 u32 deinterlace_diag; /* 0x0a4 */ 53 u32 deinterlace_tempdiff; /* 0x0a8 */ 54 u32 deinterlace_sawtooth; /* 0x0ac */ 55 u32 deinterlace_spatcomp; /* 0x0b0 */ 56 u32 deinterlace_burstlen; /* 0x0b4 */ 57 u32 deinterlace_preluma; /* 0x0b8 */ 58 u32 deinterlace_tile_addr; /* 0x0bc */ 59 u32 deinterlace_tile_stride; /* 0x0c0 */ 60 u8 res3[0x0c]; /* 0x0c4 */ 61 u32 wb_stride_enable; /* 0x0d0 */ 62 u32 ch3_stride; /* 0x0d4 */ 63 u32 ch4_stride; /* 0x0d8 */ 64 u32 ch5_stride; /* 0x0dc */ 65 u32 fe_3d_ctrl; /* 0x0e0 */ 66 u32 fe_3d_ch0_addr; /* 0x0e4 */ 67 u32 fe_3d_ch1_addr; /* 0x0e8 */ 68 u32 fe_3d_ch2_addr; /* 0x0ec */ 69 u32 fe_3d_ch0_offset; /* 0x0f0 */ 70 u32 fe_3d_ch1_offset; /* 0x0f4 */ 71 u32 fe_3d_ch2_offset; /* 0x0f8 */ 72 u8 res4[0x04]; /* 0x0fc */ 73 u32 ch0_insize; /* 0x100 */ 74 u32 ch0_outsize; /* 0x104 */ 75 u32 ch0_horzfact; /* 0x108 */ 76 u32 ch0_vertfact; /* 0x10c */ 77 u32 ch0_horzphase; /* 0x110 */ 78 u32 ch0_vertphase0; /* 0x114 */ 79 u32 ch0_vertphase1; /* 0x118 */ 80 u8 res5[0x04]; /* 0x11c */ 81 u32 ch0_horztapoffset0; /* 0x120 */ 82 u32 ch0_horztapoffset1; /* 0x124 */ 83 u32 ch0_verttapoffset; /* 0x128 */ 84 u8 res6[0xd4]; /* 0x12c */ 85 u32 ch1_insize; /* 0x200 */ 86 u32 ch1_outsize; /* 0x204 */ 87 u32 ch1_horzfact; /* 0x208 */ 88 u32 ch1_vertfact; /* 0x20c */ 89 u32 ch1_horzphase; /* 0x210 */ 90 u32 ch1_vertphase0; /* 0x214 */ 91 u32 ch1_vertphase1; /* 0x218 */ 92 u8 res7[0x04]; /* 0x21c */ 93 u32 ch1_horztapoffset0; /* 0x220 */ 94 u32 ch1_horztapoffset1; /* 0x224 */ 95 u32 ch1_verttapoffset; /* 0x228 */ 96 u8 res8[0x1d4]; /* 0x22c */ 97 u32 ch0_horzcoef0[32]; /* 0x400 */ 98 u32 ch0_horzcoef1[32]; /* 0x480 */ 99 u32 ch0_vertcoef[32]; /* 0x500 */ 100 u8 res9[0x80]; /* 0x580 */ 101 u32 ch1_horzcoef0[32]; /* 0x600 */ 102 u32 ch1_horzcoef1[32]; /* 0x680 */ 103 u32 ch1_vertcoef[32]; /* 0x700 */ 104 u8 res10[0x280]; /* 0x780 */ 105 u32 vpp_enable; /* 0xa00 */ 106 u32 vpp_dcti; /* 0xa04 */ 107 u32 vpp_lp1; /* 0xa08 */ 108 u32 vpp_lp2; /* 0xa0c */ 109 u32 vpp_wle; /* 0xa10 */ 110 u32 vpp_ble; /* 0xa14 */ 111 }; 112 113 struct sunxi_de_be_reg { 114 u8 res0[0x800]; /* 0x000 */ 115 u32 mode; /* 0x800 */ 116 u32 backcolor; /* 0x804 */ 117 u32 disp_size; /* 0x808 */ 118 u8 res1[0x4]; /* 0x80c */ 119 u32 layer0_size; /* 0x810 */ 120 u32 layer1_size; /* 0x814 */ 121 u32 layer2_size; /* 0x818 */ 122 u32 layer3_size; /* 0x81c */ 123 u32 layer0_pos; /* 0x820 */ 124 u32 layer1_pos; /* 0x824 */ 125 u32 layer2_pos; /* 0x828 */ 126 u32 layer3_pos; /* 0x82c */ 127 u8 res2[0x10]; /* 0x830 */ 128 u32 layer0_stride; /* 0x840 */ 129 u32 layer1_stride; /* 0x844 */ 130 u32 layer2_stride; /* 0x848 */ 131 u32 layer3_stride; /* 0x84c */ 132 u32 layer0_addr_low32b; /* 0x850 */ 133 u32 layer1_addr_low32b; /* 0x854 */ 134 u32 layer2_addr_low32b; /* 0x858 */ 135 u32 layer3_addr_low32b; /* 0x85c */ 136 u32 layer0_addr_high4b; /* 0x860 */ 137 u32 layer1_addr_high4b; /* 0x864 */ 138 u32 layer2_addr_high4b; /* 0x868 */ 139 u32 layer3_addr_high4b; /* 0x86c */ 140 u32 reg_ctrl; /* 0x870 */ 141 u8 res3[0xc]; /* 0x874 */ 142 u32 color_key_max; /* 0x880 */ 143 u32 color_key_min; /* 0x884 */ 144 u32 color_key_config; /* 0x888 */ 145 u8 res4[0x4]; /* 0x88c */ 146 u32 layer0_attr0_ctrl; /* 0x890 */ 147 u32 layer1_attr0_ctrl; /* 0x894 */ 148 u32 layer2_attr0_ctrl; /* 0x898 */ 149 u32 layer3_attr0_ctrl; /* 0x89c */ 150 u32 layer0_attr1_ctrl; /* 0x8a0 */ 151 u32 layer1_attr1_ctrl; /* 0x8a4 */ 152 u32 layer2_attr1_ctrl; /* 0x8a8 */ 153 u32 layer3_attr1_ctrl; /* 0x8ac */ 154 u8 res5[0x110]; /* 0x8b0 */ 155 u32 output_color_ctrl; /* 0x9c0 */ 156 u8 res6[0xc]; /* 0x9c4 */ 157 u32 output_color_coef[12]; /* 0x9d0 */ 158 }; 159 160 struct sunxi_hdmi_reg { 161 u32 version_id; /* 0x000 */ 162 u32 ctrl; /* 0x004 */ 163 u32 irq; /* 0x008 */ 164 u32 hpd; /* 0x00c */ 165 u32 video_ctrl; /* 0x010 */ 166 u32 video_size; /* 0x014 */ 167 u32 video_bp; /* 0x018 */ 168 u32 video_fp; /* 0x01c */ 169 u32 video_spw; /* 0x020 */ 170 u32 video_polarity; /* 0x024 */ 171 u8 res0[0x58]; /* 0x028 */ 172 u8 avi_info_frame[0x14]; /* 0x080 */ 173 u8 res1[0x4c]; /* 0x094 */ 174 u32 qcp_packet0; /* 0x0e0 */ 175 u32 qcp_packet1; /* 0x0e4 */ 176 u8 res2[0x118]; /* 0x0e8 */ 177 u32 pad_ctrl0; /* 0x200 */ 178 u32 pad_ctrl1; /* 0x204 */ 179 u32 pll_ctrl; /* 0x208 */ 180 u32 pll_dbg0; /* 0x20c */ 181 u32 pll_dbg1; /* 0x210 */ 182 u32 hpd_cec; /* 0x214 */ 183 u8 res3[0x28]; /* 0x218 */ 184 u8 vendor_info_frame[0x14]; /* 0x240 */ 185 u8 res4[0x9c]; /* 0x254 */ 186 u32 pkt_ctrl0; /* 0x2f0 */ 187 u32 pkt_ctrl1; /* 0x2f4 */ 188 u8 res5[0x8]; /* 0x2f8 */ 189 u32 unknown; /* 0x300 */ 190 u8 res6[0xc]; /* 0x304 */ 191 u32 audio_sample_count; /* 0x310 */ 192 u8 res7[0xec]; /* 0x314 */ 193 u32 audio_tx_fifo; /* 0x400 */ 194 u8 res8[0xfc]; /* 0x404 */ 195 #ifndef CONFIG_MACH_SUN6I 196 u32 ddc_ctrl; /* 0x500 */ 197 u32 ddc_addr; /* 0x504 */ 198 u32 ddc_int_mask; /* 0x508 */ 199 u32 ddc_int_status; /* 0x50c */ 200 u32 ddc_fifo_ctrl; /* 0x510 */ 201 u32 ddc_fifo_status; /* 0x514 */ 202 u32 ddc_fifo_data; /* 0x518 */ 203 u32 ddc_byte_count; /* 0x51c */ 204 u32 ddc_cmnd; /* 0x520 */ 205 u32 ddc_exreg; /* 0x524 */ 206 u32 ddc_clock; /* 0x528 */ 207 u8 res9[0x14]; /* 0x52c */ 208 u32 ddc_line_ctrl; /* 0x540 */ 209 #else 210 u32 ddc_ctrl; /* 0x500 */ 211 u32 ddc_exreg; /* 0x504 */ 212 u32 ddc_cmnd; /* 0x508 */ 213 u32 ddc_addr; /* 0x50c */ 214 u32 ddc_int_mask; /* 0x510 */ 215 u32 ddc_int_status; /* 0x514 */ 216 u32 ddc_fifo_ctrl; /* 0x518 */ 217 u32 ddc_fifo_status; /* 0x51c */ 218 u32 ddc_clock; /* 0x520 */ 219 u32 ddc_timeout; /* 0x524 */ 220 u8 res9[0x18]; /* 0x528 */ 221 u32 ddc_dbg; /* 0x540 */ 222 u8 res10[0x3c]; /* 0x544 */ 223 u32 ddc_fifo_data; /* 0x580 */ 224 #endif 225 }; 226 227 /* 228 * This is based on the A10s User Manual, and the A10s only supports 229 * composite video and not vga like the A10 / A20 does, still other 230 * than the removed vga out capability the tvencoder seems to be the same. 231 * "unknown#" registers are registers which are used in the A10 kernel code, 232 * but not documented in the A10s User Manual. 233 */ 234 struct sunxi_tve_reg { 235 u32 gctrl; /* 0x000 */ 236 u32 cfg0; /* 0x004 */ 237 u32 dac_cfg0; /* 0x008 */ 238 u32 filter; /* 0x00c */ 239 u32 chroma_freq; /* 0x010 */ 240 u32 porch_num; /* 0x014 */ 241 u32 unknown0; /* 0x018 */ 242 u32 line_num; /* 0x01c */ 243 u32 blank_black_level; /* 0x020 */ 244 u32 unknown1; /* 0x024, seems to be 1 byte per dac */ 245 u8 res0[0x08]; /* 0x028 */ 246 u32 auto_detect_en; /* 0x030 */ 247 u32 auto_detect_int_status; /* 0x034 */ 248 u32 auto_detect_status; /* 0x038 */ 249 u32 auto_detect_debounce; /* 0x03c */ 250 u32 csc_reg0; /* 0x040 */ 251 u32 csc_reg1; /* 0x044 */ 252 u32 csc_reg2; /* 0x048 */ 253 u32 csc_reg3; /* 0x04c */ 254 u8 res1[0xb0]; /* 0x050 */ 255 u32 color_burst; /* 0x100 */ 256 u32 vsync_num; /* 0x104 */ 257 u32 notch_freq; /* 0x108 */ 258 u32 cbr_level; /* 0x10c */ 259 u32 burst_phase; /* 0x110 */ 260 u32 burst_width; /* 0x114 */ 261 u32 unknown2; /* 0x118 */ 262 u32 sync_vbi_level; /* 0x11c */ 263 u32 white_level; /* 0x120 */ 264 u32 active_num; /* 0x124 */ 265 u32 chroma_bw_gain; /* 0x128 */ 266 u32 notch_width; /* 0x12c */ 267 u32 resync_num; /* 0x130 */ 268 u32 slave_para; /* 0x134 */ 269 u32 cfg1; /* 0x138 */ 270 u32 cfg2; /* 0x13c */ 271 }; 272 273 /* 274 * DE-FE register constants. 275 */ 276 #define SUNXI_DE_FE_WIDTH(x) (((x) - 1) << 0) 277 #define SUNXI_DE_FE_HEIGHT(y) (((y) - 1) << 16) 278 #define SUNXI_DE_FE_FACTOR_INT(n) ((n) << 16) 279 #define SUNXI_DE_FE_ENABLE_EN (1 << 0) 280 #define SUNXI_DE_FE_FRAME_CTRL_REG_RDY (1 << 0) 281 #define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY (1 << 1) 282 #define SUNXI_DE_FE_FRAME_CTRL_FRM_START (1 << 16) 283 #define SUNXI_DE_FE_BYPASS_CSC_BYPASS (1 << 1) 284 #define SUNXI_DE_FE_INPUT_FMT_ARGB8888 0x00000151 285 #define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888 0x00000002 286 287 /* 288 * DE-BE register constants. 289 */ 290 #define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0) 291 #define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16) 292 #define SUNXI_DE_BE_MODE_ENABLE (1 << 0) 293 #define SUNXI_DE_BE_MODE_START (1 << 1) 294 #define SUNXI_DE_BE_MODE_DEFLICKER_ENABLE (1 << 4) 295 #define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8) 296 #define SUNXI_DE_BE_MODE_INTERLACE_ENABLE (1 << 28) 297 #define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5) 298 #define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0) 299 #define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0 0x00000002 300 #define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8) 301 #define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE 1 302 303 /* 304 * HDMI register constants. 305 */ 306 #define SUNXI_HDMI_X(x) (((x) - 1) << 0) 307 #define SUNXI_HDMI_Y(y) (((y) - 1) << 16) 308 #define SUNXI_HDMI_CTRL_ENABLE (1 << 31) 309 #define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0) 310 #define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1) 311 #define SUNXI_HDMI_IRQ_STATUS_BITS 0x73 312 #define SUNXI_HDMI_HPD_DETECT (1 << 0) 313 #define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31) 314 #define SUNXI_HDMI_VIDEO_CTRL_HDMI (1 << 30) 315 #define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0) 316 #define SUNXI_HDMI_VIDEO_POL_VER (1 << 1) 317 #define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16) 318 #define SUNXI_HDMI_QCP_PACKET0 3 319 #define SUNXI_HDMI_QCP_PACKET1 0 320 321 #ifdef CONFIG_MACH_SUN6I 322 #define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f 323 #define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff 324 #else 325 #define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000 326 #define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000 327 #endif 328 329 #ifdef CONFIG_MACH_SUN4I 330 #define SUNXI_HDMI_PAD_CTRL1 0x00d8c820 331 #elif defined CONFIG_MACH_SUN6I 332 #define SUNXI_HDMI_PAD_CTRL1 0x01ded030 333 #else 334 #define SUNXI_HDMI_PAD_CTRL1 0x00d8c830 335 #endif 336 #define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6) 337 338 #ifdef CONFIG_MACH_SUN6I 339 #define SUNXI_HDMI_PLL_CTRL 0xba48a308 340 #define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4) 341 #else 342 #define SUNXI_HDMI_PLL_CTRL 0xfa4ef708 343 #define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4) 344 #endif 345 #define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4) 346 347 #define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21) 348 #define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21) 349 350 #define SUNXI_HDMI_PKT_CTRL0 0x00000f21 351 #define SUNXI_HDMI_PKT_CTRL1 0x0000000f 352 #define SUNXI_HDMI_UNKNOWN_INPUT_SYNC 0x08000000 353 354 #ifdef CONFIG_MACH_SUN6I 355 #define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 0) 356 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE (1 << 4) 357 #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE (1 << 6) 358 #define SUNXI_HMDI_DDC_CTRL_START (1 << 27) 359 #define SUNXI_HMDI_DDC_CTRL_RESET (1 << 31) 360 #else 361 #define SUNXI_HMDI_DDC_CTRL_RESET (1 << 0) 362 /* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */ 363 #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE 0 364 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE 0 365 #define SUNXI_HMDI_DDC_CTRL_START (1 << 30) 366 #define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 31) 367 #endif 368 369 #ifdef CONFIG_MACH_SUN6I 370 #define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0xa0 << 0) 371 #else 372 #define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0) 373 #endif 374 #define SUNXI_HMDI_DDC_ADDR_OFFSET(n) (((n) & 0xff) << 8) 375 #define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR (0x60 << 16) 376 #define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n) ((n) << 24) 377 378 #ifdef CONFIG_MACH_SUN6I 379 #define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 15) 380 #else 381 #define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 31) 382 #endif 383 384 #define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ 6 385 #define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ 7 386 387 #ifdef CONFIG_MACH_SUN6I 388 #define SUNXI_HDMI_DDC_CLOCK 0x61 389 #else 390 /* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */ 391 #define SUNXI_HDMI_DDC_CLOCK 0x0d 392 #endif 393 394 #define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8) 395 #define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9) 396 397 /* 398 * TVE register constants. 399 */ 400 #define SUNXI_TVE_GCTRL_ENABLE (1 << 0) 401 /* 402 * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed 403 * dac from tve1. When using tve1 the mux value must be written to both tve0's 404 * and tve1's gctrl reg. 405 */ 406 #define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac) (0xf << (((dac) + 1) * 4)) 407 #define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4)) 408 #define SUNXI_TVE_CFG0_VGA 0x20000000 409 #define SUNXI_TVE_CFG0_PAL 0x07030001 410 #define SUNXI_TVE_CFG0_NTSC 0x07030000 411 #define SUNXI_TVE_DAC_CFG0_VGA 0x403e1ac7 412 #ifdef CONFIG_MACH_SUN5I 413 #define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x433f0009 414 #else 415 #define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x403f0008 416 #endif 417 #define SUNXI_TVE_FILTER_COMPOSITE 0x00000120 418 #define SUNXI_TVE_CHROMA_FREQ_PAL_M 0x21e6efe3 419 #define SUNXI_TVE_CHROMA_FREQ_PAL_NC 0x21f69446 420 #define SUNXI_TVE_PORCH_NUM_PAL 0x008a0018 421 #define SUNXI_TVE_PORCH_NUM_NTSC 0x00760020 422 #define SUNXI_TVE_LINE_NUM_PAL 0x00160271 423 #define SUNXI_TVE_LINE_NUM_NTSC 0x0016020d 424 #define SUNXI_TVE_BLANK_BLACK_LEVEL_PAL 0x00fc00fc 425 #define SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC 0x00f0011a 426 #define SUNXI_TVE_UNKNOWN1_VGA 0x00000000 427 #define SUNXI_TVE_UNKNOWN1_COMPOSITE 0x18181818 428 #define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac) (1 << ((dac) + 0)) 429 #define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac) (1 << ((dac) + 16)) 430 #define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac) (1 << ((dac) + 0)) 431 #define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac) ((dac) * 8) 432 #define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac) (3 << ((dac) * 8)) 433 #define SUNXI_TVE_AUTO_DETECT_STATUS_NONE 0 434 #define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED 1 435 #define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3 436 #define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8) 437 #define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8)) 438 #define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31) 439 #define SUNXI_TVE_CSC_REG0 0x08440832 440 #define SUNXI_TVE_CSC_REG1 0x3b6dace1 441 #define SUNXI_TVE_CSC_REG2 0x0e1d13dc 442 #define SUNXI_TVE_CSC_REG3 0x00108080 443 #define SUNXI_TVE_COLOR_BURST_PAL_M 0x00000000 444 #define SUNXI_TVE_CBR_LEVEL_PAL 0x00002828 445 #define SUNXI_TVE_CBR_LEVEL_NTSC 0x0000004f 446 #define SUNXI_TVE_BURST_PHASE_NTSC 0x00000000 447 #define SUNXI_TVE_BURST_WIDTH_COMPOSITE 0x0016447e 448 #define SUNXI_TVE_UNKNOWN2_PAL 0x0000e0e0 449 #define SUNXI_TVE_UNKNOWN2_NTSC 0x0000a0a0 450 #define SUNXI_TVE_SYNC_VBI_LEVEL_NTSC 0x001000f0 451 #define SUNXI_TVE_ACTIVE_NUM_COMPOSITE 0x000005a0 452 #define SUNXI_TVE_CHROMA_BW_GAIN_COMP 0x00000002 453 #define SUNXI_TVE_NOTCH_WIDTH_COMPOSITE 0x00000101 454 #define SUNXI_TVE_RESYNC_NUM_PAL 0x800d000c 455 #define SUNXI_TVE_RESYNC_NUM_NTSC 0x000e000c 456 #define SUNXI_TVE_SLAVE_PARA_COMPOSITE 0x00000000 457 458 int sunxi_simplefb_setup(void *blob); 459 460 #endif /* _SUNXI_DISPLAY_H */ 461