1 /*
2  * Sunxi platform display controller register and constant defines
3  *
4  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 #ifndef _SUNXI_DISPLAY_H
10 #define _SUNXI_DISPLAY_H
11 
12 struct sunxi_de_fe_reg {
13 	u32 enable;			/* 0x000 */
14 	u32 frame_ctrl;			/* 0x004 */
15 	u32 bypass;			/* 0x008 */
16 	u32 algorithm_sel;		/* 0x00c */
17 	u32 line_int_ctrl;		/* 0x010 */
18 	u8 res0[0x0c];			/* 0x014 */
19 	u32 ch0_addr;			/* 0x020 */
20 	u32 ch1_addr;			/* 0x024 */
21 	u32 ch2_addr;			/* 0x028 */
22 	u32 field_sequence;		/* 0x02c */
23 	u32 ch0_offset;			/* 0x030 */
24 	u32 ch1_offset;			/* 0x034 */
25 	u32 ch2_offset;			/* 0x038 */
26 	u8 res1[0x04];			/* 0x03c */
27 	u32 ch0_stride;			/* 0x040 */
28 	u32 ch1_stride;			/* 0x044 */
29 	u32 ch2_stride;			/* 0x048 */
30 	u32 input_fmt;			/* 0x04c */
31 	u32 ch3_addr;			/* 0x050 */
32 	u32 ch4_addr;			/* 0x054 */
33 	u32 ch5_addr;			/* 0x058 */
34 	u32 output_fmt;			/* 0x05c */
35 	u32 int_enable;			/* 0x060 */
36 	u32 int_status;			/* 0x064 */
37 	u32 status;			/* 0x068 */
38 	u8 res2[0x04];			/* 0x06c */
39 	u32 csc_coef00;			/* 0x070 */
40 	u32 csc_coef01;			/* 0x074 */
41 	u32 csc_coef02;			/* 0x078 */
42 	u32 csc_coef03;			/* 0x07c */
43 	u32 csc_coef10;			/* 0x080 */
44 	u32 csc_coef11;			/* 0x084 */
45 	u32 csc_coef12;			/* 0x088 */
46 	u32 csc_coef13;			/* 0x08c */
47 	u32 csc_coef20;			/* 0x090 */
48 	u32 csc_coef21;			/* 0x094 */
49 	u32 csc_coef22;			/* 0x098 */
50 	u32 csc_coef23;			/* 0x09c */
51 	u32 deinterlace_ctrl;		/* 0x0a0 */
52 	u32 deinterlace_diag;		/* 0x0a4 */
53 	u32 deinterlace_tempdiff;	/* 0x0a8 */
54 	u32 deinterlace_sawtooth;	/* 0x0ac */
55 	u32 deinterlace_spatcomp;	/* 0x0b0 */
56 	u32 deinterlace_burstlen;	/* 0x0b4 */
57 	u32 deinterlace_preluma;	/* 0x0b8 */
58 	u32 deinterlace_tile_addr;	/* 0x0bc */
59 	u32 deinterlace_tile_stride;	/* 0x0c0 */
60 	u8 res3[0x0c];			/* 0x0c4 */
61 	u32 wb_stride_enable;		/* 0x0d0 */
62 	u32 ch3_stride;			/* 0x0d4 */
63 	u32 ch4_stride;			/* 0x0d8 */
64 	u32 ch5_stride;			/* 0x0dc */
65 	u32 fe_3d_ctrl;			/* 0x0e0 */
66 	u32 fe_3d_ch0_addr;		/* 0x0e4 */
67 	u32 fe_3d_ch1_addr;		/* 0x0e8 */
68 	u32 fe_3d_ch2_addr;		/* 0x0ec */
69 	u32 fe_3d_ch0_offset;		/* 0x0f0 */
70 	u32 fe_3d_ch1_offset;		/* 0x0f4 */
71 	u32 fe_3d_ch2_offset;		/* 0x0f8 */
72 	u8 res4[0x04];			/* 0x0fc */
73 	u32 ch0_insize;			/* 0x100 */
74 	u32 ch0_outsize;		/* 0x104 */
75 	u32 ch0_horzfact;		/* 0x108 */
76 	u32 ch0_vertfact;		/* 0x10c */
77 	u32 ch0_horzphase;		/* 0x110 */
78 	u32 ch0_vertphase0;		/* 0x114 */
79 	u32 ch0_vertphase1;		/* 0x118 */
80 	u8 res5[0x04];			/* 0x11c */
81 	u32 ch0_horztapoffset0;		/* 0x120 */
82 	u32 ch0_horztapoffset1;		/* 0x124 */
83 	u32 ch0_verttapoffset;		/* 0x128 */
84 	u8 res6[0xd4];			/* 0x12c */
85 	u32 ch1_insize;			/* 0x200 */
86 	u32 ch1_outsize;		/* 0x204 */
87 	u32 ch1_horzfact;		/* 0x208 */
88 	u32 ch1_vertfact;		/* 0x20c */
89 	u32 ch1_horzphase;		/* 0x210 */
90 	u32 ch1_vertphase0;		/* 0x214 */
91 	u32 ch1_vertphase1;		/* 0x218 */
92 	u8 res7[0x04];			/* 0x21c */
93 	u32 ch1_horztapoffset0;		/* 0x220 */
94 	u32 ch1_horztapoffset1;		/* 0x224 */
95 	u32 ch1_verttapoffset;		/* 0x228 */
96 	u8 res8[0x1d4];			/* 0x22c */
97 	u32 ch0_horzcoef0[32];		/* 0x400 */
98 	u32 ch0_horzcoef1[32];		/* 0x480 */
99 	u32 ch0_vertcoef[32];		/* 0x500 */
100 	u8 res9[0x80];			/* 0x580 */
101 	u32 ch1_horzcoef0[32];		/* 0x600 */
102 	u32 ch1_horzcoef1[32];		/* 0x680 */
103 	u32 ch1_vertcoef[32];		/* 0x700 */
104 	u8 res10[0x280];		/* 0x780 */
105 	u32 vpp_enable;			/* 0xa00 */
106 	u32 vpp_dcti;			/* 0xa04 */
107 	u32 vpp_lp1;			/* 0xa08 */
108 	u32 vpp_lp2;			/* 0xa0c */
109 	u32 vpp_wle;			/* 0xa10 */
110 	u32 vpp_ble;			/* 0xa14 */
111 };
112 
113 struct sunxi_de_be_reg {
114 	u8 res0[0x800];			/* 0x000 */
115 	u32 mode;			/* 0x800 */
116 	u32 backcolor;			/* 0x804 */
117 	u32 disp_size;			/* 0x808 */
118 	u8 res1[0x4];			/* 0x80c */
119 	u32 layer0_size;		/* 0x810 */
120 	u32 layer1_size;		/* 0x814 */
121 	u32 layer2_size;		/* 0x818 */
122 	u32 layer3_size;		/* 0x81c */
123 	u32 layer0_pos;			/* 0x820 */
124 	u32 layer1_pos;			/* 0x824 */
125 	u32 layer2_pos;			/* 0x828 */
126 	u32 layer3_pos;			/* 0x82c */
127 	u8 res2[0x10];			/* 0x830 */
128 	u32 layer0_stride;		/* 0x840 */
129 	u32 layer1_stride;		/* 0x844 */
130 	u32 layer2_stride;		/* 0x848 */
131 	u32 layer3_stride;		/* 0x84c */
132 	u32 layer0_addr_low32b;		/* 0x850 */
133 	u32 layer1_addr_low32b;		/* 0x854 */
134 	u32 layer2_addr_low32b;		/* 0x858 */
135 	u32 layer3_addr_low32b;		/* 0x85c */
136 	u32 layer0_addr_high4b;		/* 0x860 */
137 	u32 layer1_addr_high4b;		/* 0x864 */
138 	u32 layer2_addr_high4b;		/* 0x868 */
139 	u32 layer3_addr_high4b;		/* 0x86c */
140 	u32 reg_ctrl;			/* 0x870 */
141 	u8 res3[0xc];			/* 0x874 */
142 	u32 color_key_max;		/* 0x880 */
143 	u32 color_key_min;		/* 0x884 */
144 	u32 color_key_config;		/* 0x888 */
145 	u8 res4[0x4];			/* 0x88c */
146 	u32 layer0_attr0_ctrl;		/* 0x890 */
147 	u32 layer1_attr0_ctrl;		/* 0x894 */
148 	u32 layer2_attr0_ctrl;		/* 0x898 */
149 	u32 layer3_attr0_ctrl;		/* 0x89c */
150 	u32 layer0_attr1_ctrl;		/* 0x8a0 */
151 	u32 layer1_attr1_ctrl;		/* 0x8a4 */
152 	u32 layer2_attr1_ctrl;		/* 0x8a8 */
153 	u32 layer3_attr1_ctrl;		/* 0x8ac */
154 };
155 
156 struct sunxi_lcdc_reg {
157 	u32 ctrl;			/* 0x00 */
158 	u32 int0;			/* 0x04 */
159 	u32 int1;			/* 0x08 */
160 	u8 res0[0x04];			/* 0x0c */
161 	u32 tcon0_frm_ctrl;		/* 0x10 */
162 	u32 tcon0_frm_seed[6];		/* 0x14 */
163 	u32 tcon0_frm_table[4];		/* 0x2c */
164 	u8 res1[4];			/* 0x3c */
165 	u32 tcon0_ctrl;			/* 0x40 */
166 	u32 tcon0_dclk;			/* 0x44 */
167 	u32 tcon0_timing_active;	/* 0x48 */
168 	u32 tcon0_timing_h;		/* 0x4c */
169 	u32 tcon0_timing_v;		/* 0x50 */
170 	u32 tcon0_timing_sync;		/* 0x54 */
171 	u32 tcon0_hv_intf;		/* 0x58 */
172 	u8 res2[0x04];			/* 0x5c */
173 	u32 tcon0_cpu_intf;		/* 0x60 */
174 	u32 tcon0_cpu_wr_dat;		/* 0x64 */
175 	u32 tcon0_cpu_rd_dat0;		/* 0x68 */
176 	u32 tcon0_cpu_rd_dat1;		/* 0x6c */
177 	u32 tcon0_ttl_timing0;		/* 0x70 */
178 	u32 tcon0_ttl_timing1;		/* 0x74 */
179 	u32 tcon0_ttl_timing2;		/* 0x78 */
180 	u32 tcon0_ttl_timing3;		/* 0x7c */
181 	u32 tcon0_ttl_timing4;		/* 0x80 */
182 	u32 tcon0_lvds_intf;		/* 0x84 */
183 	u32 tcon0_io_polarity;		/* 0x88 */
184 	u32 tcon0_io_tristate;		/* 0x8c */
185 	u32 tcon1_ctrl;			/* 0x90 */
186 	u32 tcon1_timing_source;	/* 0x94 */
187 	u32 tcon1_timing_scale;		/* 0x98 */
188 	u32 tcon1_timing_out;		/* 0x9c */
189 	u32 tcon1_timing_h;		/* 0xa0 */
190 	u32 tcon1_timing_v;		/* 0xa4 */
191 	u32 tcon1_timing_sync;		/* 0xa8 */
192 	u8 res3[0x44];			/* 0xac */
193 	u32 tcon1_io_polarity;		/* 0xf0 */
194 	u32 tcon1_io_tristate;		/* 0xf4 */
195 	u8 res4[0x128];			/* 0xf8 */
196 	u32 lvds_ana0;			/* 0x220 */
197 	u32 lvds_ana1;			/* 0x224 */
198 };
199 
200 struct sunxi_hdmi_reg {
201 	u32 version_id;			/* 0x000 */
202 	u32 ctrl;			/* 0x004 */
203 	u32 irq;			/* 0x008 */
204 	u32 hpd;			/* 0x00c */
205 	u32 video_ctrl;			/* 0x010 */
206 	u32 video_size;			/* 0x014 */
207 	u32 video_bp;			/* 0x018 */
208 	u32 video_fp;			/* 0x01c */
209 	u32 video_spw;			/* 0x020 */
210 	u32 video_polarity;		/* 0x024 */
211 	u8 res0[0x58];			/* 0x028 */
212 	u8 avi_info_frame[0x14];	/* 0x080 */
213 	u8 res1[0x4c];			/* 0x094 */
214 	u32 qcp_packet0;		/* 0x0e0 */
215 	u32 qcp_packet1;		/* 0x0e4 */
216 	u8 res2[0x118];			/* 0x0e8 */
217 	u32 pad_ctrl0;			/* 0x200 */
218 	u32 pad_ctrl1;			/* 0x204 */
219 	u32 pll_ctrl;			/* 0x208 */
220 	u32 pll_dbg0;			/* 0x20c */
221 	u32 pll_dbg1;			/* 0x210 */
222 	u32 hpd_cec;			/* 0x214 */
223 	u8 res3[0x28];			/* 0x218 */
224 	u8 vendor_info_frame[0x14];	/* 0x240 */
225 	u8 res4[0x9c];			/* 0x254 */
226 	u32 pkt_ctrl0;			/* 0x2f0 */
227 	u32 pkt_ctrl1;			/* 0x2f4 */
228 	u8 res5[0x8];			/* 0x2f8 */
229 	u32 unknown;			/* 0x300 */
230 	u8 res6[0xc];			/* 0x304 */
231 	u32 audio_sample_count;		/* 0x310 */
232 	u8 res7[0xec];			/* 0x314 */
233 	u32 audio_tx_fifo;		/* 0x400 */
234 	u8 res8[0xfc];			/* 0x404 */
235 #ifndef CONFIG_MACH_SUN6I
236 	u32 ddc_ctrl;			/* 0x500 */
237 	u32 ddc_addr;			/* 0x504 */
238 	u32 ddc_int_mask;		/* 0x508 */
239 	u32 ddc_int_status;		/* 0x50c */
240 	u32 ddc_fifo_ctrl;		/* 0x510 */
241 	u32 ddc_fifo_status;		/* 0x514 */
242 	u32 ddc_fifo_data;		/* 0x518 */
243 	u32 ddc_byte_count;		/* 0x51c */
244 	u32 ddc_cmnd;			/* 0x520 */
245 	u32 ddc_exreg;			/* 0x524 */
246 	u32 ddc_clock;			/* 0x528 */
247 	u8 res9[0x14];			/* 0x52c */
248 	u32 ddc_line_ctrl;		/* 0x540 */
249 #else
250 	u32 ddc_ctrl;			/* 0x500 */
251 	u32 ddc_exreg;			/* 0x504 */
252 	u32 ddc_cmnd;			/* 0x508 */
253 	u32 ddc_addr;			/* 0x50c */
254 	u32 ddc_int_mask;		/* 0x510 */
255 	u32 ddc_int_status;		/* 0x514 */
256 	u32 ddc_fifo_ctrl;		/* 0x518 */
257 	u32 ddc_fifo_status;		/* 0x51c */
258 	u32 ddc_clock;			/* 0x520 */
259 	u32 ddc_timeout;		/* 0x524 */
260 	u8 res9[0x18];			/* 0x528 */
261 	u32 ddc_dbg;			/* 0x540 */
262 	u8 res10[0x3c];			/* 0x544 */
263 	u32 ddc_fifo_data;		/* 0x580 */
264 #endif
265 };
266 
267 /*
268  * This is based on the A10s User Manual, and the A10s only supports
269  * composite video and not vga like the A10 / A20 does, still other
270  * than the removed vga out capability the tvencoder seems to be the same.
271  * "unknown#" registers are registers which are used in the A10 kernel code,
272  * but not documented in the A10s User Manual.
273  */
274 struct sunxi_tve_reg {
275 	u32 gctrl;			/* 0x000 */
276 	u32 cfg0;			/* 0x004 */
277 	u32 dac_cfg0;			/* 0x008 */
278 	u32 filter;			/* 0x00c */
279 	u32 chroma_freq;		/* 0x010 */
280 	u32 porch_num;			/* 0x014 */
281 	u32 unknown0;			/* 0x018 */
282 	u32 line_num;			/* 0x01c */
283 	u32 blank_black_level;		/* 0x020 */
284 	u32 unknown1;			/* 0x024, seems to be 1 byte per dac */
285 	u8 res0[0x08];			/* 0x028 */
286 	u32 auto_detect_en;		/* 0x030 */
287 	u32 auto_detect_int_status;	/* 0x034 */
288 	u32 auto_detect_status;		/* 0x038 */
289 	u32 auto_detect_debounce;	/* 0x03c */
290 	u32 csc_reg0;			/* 0x040 */
291 	u32 csc_reg1;			/* 0x044 */
292 	u32 csc_reg2;			/* 0x048 */
293 	u32 csc_reg3;			/* 0x04c */
294 	u8 res1[0xb0];			/* 0x050 */
295 	u32 color_burst;		/* 0x100 */
296 	u32 vsync_num;			/* 0x104 */
297 	u32 notch_freq;			/* 0x108 */
298 	u32 cbr_level;			/* 0x10c */
299 	u32 burst_phase;		/* 0x110 */
300 	u32 burst_width;		/* 0x114 */
301 	u8 res2[0x04];			/* 0x118 */
302 	u32 sync_vbi_level;		/* 0x11c */
303 	u32 white_level;		/* 0x120 */
304 	u32 active_num;			/* 0x124 */
305 	u32 chroma_bw_gain;		/* 0x128 */
306 	u32 notch_width;		/* 0x12c */
307 	u32 resync_num;			/* 0x130 */
308 	u32 slave_para;			/* 0x134 */
309 	u32 cfg1;			/* 0x138 */
310 	u32 cfg2;			/* 0x13c */
311 };
312 
313 /*
314  * DE-FE register constants.
315  */
316 #define SUNXI_DE_FE_WIDTH(x)			(((x) - 1) << 0)
317 #define SUNXI_DE_FE_HEIGHT(y)			(((y) - 1) << 16)
318 #define SUNXI_DE_FE_FACTOR_INT(n)		((n) << 16)
319 #define SUNXI_DE_FE_ENABLE_EN			(1 << 0)
320 #define SUNXI_DE_FE_FRAME_CTRL_REG_RDY		(1 << 0)
321 #define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY		(1 << 1)
322 #define SUNXI_DE_FE_FRAME_CTRL_FRM_START	(1 << 16)
323 #define SUNXI_DE_FE_BYPASS_CSC_BYPASS		(1 << 1)
324 #define SUNXI_DE_FE_INPUT_FMT_ARGB8888		0x00000151
325 #define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888		0x00000002
326 
327 /*
328  * DE-BE register constants.
329  */
330 #define SUNXI_DE_BE_WIDTH(x)			(((x) - 1) << 0)
331 #define SUNXI_DE_BE_HEIGHT(y)			(((y) - 1) << 16)
332 #define SUNXI_DE_BE_MODE_ENABLE			(1 << 0)
333 #define SUNXI_DE_BE_MODE_START			(1 << 1)
334 #define SUNXI_DE_BE_MODE_LAYER0_ENABLE		(1 << 8)
335 #define SUNXI_DE_BE_LAYER_STRIDE(x)		((x) << 5)
336 #define SUNXI_DE_BE_REG_CTRL_LOAD_REGS		(1 << 0)
337 #define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0		0x00000002
338 #define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888	(0x09 << 8)
339 
340 /*
341  * LCDC register constants.
342  */
343 #define SUNXI_LCDC_X(x)				(((x) - 1) << 16)
344 #define SUNXI_LCDC_Y(y)				(((y) - 1) << 0)
345 #define SUNXI_LCDC_TCON_VSYNC_MASK		(1 << 24)
346 #define SUNXI_LCDC_TCON_HSYNC_MASK		(1 << 25)
347 #define SUNXI_LCDC_CTRL_IO_MAP_MASK		(1 << 0)
348 #define SUNXI_LCDC_CTRL_IO_MAP_TCON0		(0 << 0)
349 #define SUNXI_LCDC_CTRL_IO_MAP_TCON1		(1 << 0)
350 #define SUNXI_LCDC_CTRL_TCON_ENABLE		(1 << 31)
351 #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666	((1 << 31) | (0 << 4))
352 #define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565	((1 << 31) | (5 << 4))
353 #define SUNXI_LCDC_TCON0_FRM_SEED		0x11111111
354 #define SUNXI_LCDC_TCON0_FRM_TAB0		0x01010000
355 #define SUNXI_LCDC_TCON0_FRM_TAB1		0x15151111
356 #define SUNXI_LCDC_TCON0_FRM_TAB2		0x57575555
357 #define SUNXI_LCDC_TCON0_FRM_TAB3		0x7f7f7777
358 #define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
359 #define SUNXI_LCDC_TCON0_CTRL_ENABLE		(1 << 31)
360 #define SUNXI_LCDC_TCON0_DCLK_DIV(n)		((n) << 0)
361 #define SUNXI_LCDC_TCON0_DCLK_ENABLE		(0xf << 28)
362 #define SUNXI_LCDC_TCON0_TIMING_H_BP(n)		(((n) - 1) << 0)
363 #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
364 #define SUNXI_LCDC_TCON0_TIMING_V_BP(n)		(((n) - 1) << 0)
365 #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n)	(((n) * 2) << 16)
366 #ifdef CONFIG_SUNXI_GEN_SUN6I
367 #define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0	(1 << 20)
368 #else
369 #define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0	0 /* NA */
370 #endif
371 #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n)	((n) << 26)
372 #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE	(1 << 31)
373 #define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x)	((x) << 28)
374 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
375 #define SUNXI_LCDC_TCON1_CTRL_ENABLE		(1 << 31)
376 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n)		(((n) - 1) << 0)
377 #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
378 #define SUNXI_LCDC_TCON1_TIMING_V_BP(n)		(((n) - 1) << 0)
379 #define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n)	(((n) * 2) << 16)
380 #ifdef CONFIG_SUNXI_GEN_SUN6I
381 #define SUNXI_LCDC_LVDS_ANA0			0x40040320
382 #define SUNXI_LCDC_LVDS_ANA0_EN_MB		(1 << 31)
383 #define SUNXI_LCDC_LVDS_ANA0_DRVC		(1 << 24)
384 #define SUNXI_LCDC_LVDS_ANA0_DRVD(x)		((x) << 20)
385 #else
386 #define SUNXI_LCDC_LVDS_ANA0			0x3f310000
387 #define SUNXI_LCDC_LVDS_ANA0_UPDATE		(1 << 22)
388 #endif
389 #define SUNXI_LCDC_LVDS_ANA1_INIT1		(0x1f << 26 | 0x1f << 10)
390 #define SUNXI_LCDC_LVDS_ANA1_INIT2		(0x1f << 16 | 0x1f << 00)
391 
392 /*
393  * HDMI register constants.
394  */
395 #define SUNXI_HDMI_X(x)				(((x) - 1) << 0)
396 #define SUNXI_HDMI_Y(y)				(((y) - 1) << 16)
397 #define SUNXI_HDMI_CTRL_ENABLE			(1 << 31)
398 #define SUNXI_HDMI_IRQ_STATUS_FIFO_UF		(1 << 0)
399 #define SUNXI_HDMI_IRQ_STATUS_FIFO_OF		(1 << 1)
400 #define SUNXI_HDMI_IRQ_STATUS_BITS		0x73
401 #define SUNXI_HDMI_HPD_DETECT			(1 << 0)
402 #define SUNXI_HDMI_VIDEO_CTRL_ENABLE		(1 << 31)
403 #define SUNXI_HDMI_VIDEO_CTRL_HDMI		(1 << 30)
404 #define SUNXI_HDMI_VIDEO_POL_HOR		(1 << 0)
405 #define SUNXI_HDMI_VIDEO_POL_VER		(1 << 1)
406 #define SUNXI_HDMI_VIDEO_POL_TX_CLK		(0x3e0 << 16)
407 #define SUNXI_HDMI_QCP_PACKET0			3
408 #define SUNXI_HDMI_QCP_PACKET1			0
409 
410 #ifdef CONFIG_MACH_SUN6I
411 #define SUNXI_HDMI_PAD_CTRL0_HDP		0x7e80000f
412 #define SUNXI_HDMI_PAD_CTRL0_RUN		0x7e8000ff
413 #else
414 #define SUNXI_HDMI_PAD_CTRL0_HDP		0xfe800000
415 #define SUNXI_HDMI_PAD_CTRL0_RUN		0xfe800000
416 #endif
417 
418 #ifdef CONFIG_MACH_SUN4I
419 #define SUNXI_HDMI_PAD_CTRL1			0x00d8c820
420 #elif defined CONFIG_MACH_SUN6I
421 #define SUNXI_HDMI_PAD_CTRL1			0x01ded030
422 #else
423 #define SUNXI_HDMI_PAD_CTRL1			0x00d8c830
424 #endif
425 #define SUNXI_HDMI_PAD_CTRL1_HALVE		(1 << 6)
426 
427 #ifdef CONFIG_MACH_SUN6I
428 #define SUNXI_HDMI_PLL_CTRL			0xba48a308
429 #define SUNXI_HDMI_PLL_CTRL_DIV(n)		(((n) - 1) << 4)
430 #else
431 #define SUNXI_HDMI_PLL_CTRL			0xfa4ef708
432 #define SUNXI_HDMI_PLL_CTRL_DIV(n)		((n) << 4)
433 #endif
434 #define SUNXI_HDMI_PLL_CTRL_DIV_MASK		(0xf << 4)
435 
436 #define SUNXI_HDMI_PLL_DBG0_PLL3		(0 << 21)
437 #define SUNXI_HDMI_PLL_DBG0_PLL7		(1 << 21)
438 
439 #define SUNXI_HDMI_PKT_CTRL0			0x00000f21
440 #define SUNXI_HDMI_PKT_CTRL1			0x0000000f
441 #define SUNXI_HDMI_UNKNOWN_INPUT_SYNC		0x08000000
442 
443 #ifdef CONFIG_MACH_SUN6I
444 #define SUNXI_HMDI_DDC_CTRL_ENABLE		(1 << 0)
445 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE		(1 << 4)
446 #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE		(1 << 6)
447 #define SUNXI_HMDI_DDC_CTRL_START		(1 << 27)
448 #define SUNXI_HMDI_DDC_CTRL_RESET		(1 << 31)
449 #else
450 #define SUNXI_HMDI_DDC_CTRL_RESET		(1 << 0)
451 /* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */
452 #define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE		0
453 #define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE		0
454 #define SUNXI_HMDI_DDC_CTRL_START		(1 << 30)
455 #define SUNXI_HMDI_DDC_CTRL_ENABLE		(1 << 31)
456 #endif
457 
458 #ifdef CONFIG_MACH_SUN6I
459 #define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR		(0xa0 << 0)
460 #else
461 #define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR		(0x50 << 0)
462 #endif
463 #define SUNXI_HMDI_DDC_ADDR_OFFSET(n)		(((n) & 0xff) << 8)
464 #define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR		(0x60 << 16)
465 #define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n)	((n) << 24)
466 
467 #ifdef CONFIG_MACH_SUN6I
468 #define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR		(1 << 15)
469 #else
470 #define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR		(1 << 31)
471 #endif
472 
473 #define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ	6
474 #define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ	7
475 
476 #ifdef CONFIG_MACH_SUN6I
477 #define SUNXI_HDMI_DDC_CLOCK			0x61
478 #else
479 /* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */
480 #define SUNXI_HDMI_DDC_CLOCK			0x0d
481 #endif
482 
483 #define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE	(1 << 8)
484 #define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE	(1 << 9)
485 
486 /*
487  * TVE register constants.
488  */
489 #define SUNXI_TVE_GCTRL_ENABLE			(1 << 0)
490 /*
491  * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed
492  * dac from tve1. When using tve1 the mux value must be written to both tve0's
493  * and tve1's gctrl reg.
494  */
495 #define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac)	(0xf << (((dac) + 1) * 4))
496 #define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel)	((sel) << (((dac) + 1) * 4))
497 #define SUNXI_TVE_GCTRL_CFG0_VGA		0x20000000
498 #define SUNXI_TVE_GCTRL_DAC_CFG0_VGA		0x403e1ac7
499 #define SUNXI_TVE_GCTRL_UNKNOWN1_VGA		0x00000000
500 #define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac)	(1 << ((dac) + 0))
501 #define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac)	(1 << ((dac) + 16))
502 #define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac)	(1 << ((dac) + 0))
503 #define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac)	((dac) * 8)
504 #define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac)	(3 << ((dac) * 8))
505 #define SUNXI_TVE_AUTO_DETECT_STATUS_NONE	0
506 #define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED	1
507 #define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND	3
508 #define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d)	((d) * 8)
509 #define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d)	(0xf << ((d) * 8))
510 #define SUNXI_TVE_CSC_REG0_ENABLE		(1 << 31)
511 #define SUNXI_TVE_CSC_REG0			0x08440832
512 #define SUNXI_TVE_CSC_REG1			0x3b6dace1
513 #define SUNXI_TVE_CSC_REG2			0x0e1d13dc
514 #define SUNXI_TVE_CSC_REG3			0x00108080
515 
516 int sunxi_simplefb_setup(void *blob);
517 
518 #endif /* _SUNXI_DISPLAY_H */
519