1 /* 2 * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> 3 * (C) Copyright 2007-2013 4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 5 * Jerry Wang <wangflord@allwinnertech.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _SUNXI_CPU_SUN9I_H 11 #define _SUNXI_CPU_SUN9I_H 12 13 #define REGS_AHB0_BASE 0x01C00000 14 #define REGS_AHB1_BASE 0x00800000 15 #define REGS_AHB2_BASE 0x03000000 16 #define REGS_APB0_BASE 0x06000000 17 #define REGS_APB1_BASE 0x07000000 18 #define REGS_RCPUS_BASE 0x08000000 19 20 #define SUNXI_SRAM_D_BASE 0x08100000 21 22 /* AHB0 Module */ 23 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000) 24 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) 25 26 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000) 27 /* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */ 28 #define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200) 29 30 #define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000) 31 #define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000) 32 #define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000) 33 #define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000) 34 #define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000) 35 36 #define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000) 37 #define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000) 38 #define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000) 39 #define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000) 40 41 #define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000) 42 #define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000) 43 #define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000) 44 45 #define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) 46 #define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) 47 #define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000) 48 #define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000) 49 #define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000) 50 51 /* AHB1 Module */ 52 #define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) 53 #define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) 54 #define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000) 55 #define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000) 56 #define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000) 57 58 /* AHB2 Module */ 59 #define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000) 60 #define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000) 61 #define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000) 62 #define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000) 63 #define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000) 64 65 #define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000) 66 #define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000) 67 #define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000) 68 69 #define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000) 70 #define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000) 71 #define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000) 72 #define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000) 73 74 #define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000) 75 #define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000) 76 #define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000) 77 #define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000) 78 /* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */ 79 #define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100) 80 #define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000) 81 82 /* APB0 Module */ 83 #define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) 84 #define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) 85 #define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800) 86 #define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) 87 #define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) 88 #define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) 89 90 /* APB1 Module */ 91 #define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000) 92 #define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400) 93 #define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800) 94 #define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00) 95 #define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000) 96 #define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400) 97 #define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) 98 #define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) 99 #define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) 100 #define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400) 101 #define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800) 102 103 /* RCPUS Module */ 104 #define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) 105 #define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) 106 #define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00) 107 #define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400) 108 109 /* Misc. */ 110 #define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */ 111 #define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) 112 113 #ifndef __ASSEMBLY__ 114 void sunxi_board_init(void); 115 void sunxi_reset(void); 116 int sunxi_get_sid(unsigned int *sid); 117 #endif 118 119 #endif /* _SUNXI_CPU_SUN9I_H */ 120