1 /* 2 * (C) Copyright 2007-2011 3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4 * Tom Cubie <tangliang@allwinnertech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _SUNXI_CPU_SUN4I_H 10 #define _SUNXI_CPU_SUN4I_H 11 12 #define SUNXI_SRAM_A1_BASE 0x00000000 13 #define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ 14 15 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ 16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ 17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ 18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ 19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ 20 21 #define SUNXI_DE2_BASE 0x01000000 22 23 #ifdef CONFIG_MACH_SUN8I_A83T 24 #define SUNXI_CPUCFG_BASE 0x01700000 25 #endif 26 27 #define SUNXI_SRAMC_BASE 0x01c00000 28 #define SUNXI_DRAMC_BASE 0x01c01000 29 #define SUNXI_DMA_BASE 0x01c02000 30 #define SUNXI_NFC_BASE 0x01c03000 31 #define SUNXI_TS_BASE 0x01c04000 32 #define SUNXI_SPI0_BASE 0x01c05000 33 #define SUNXI_SPI1_BASE 0x01c06000 34 #define SUNXI_MS_BASE 0x01c07000 35 #define SUNXI_TVD_BASE 0x01c08000 36 #define SUNXI_CSI0_BASE 0x01c09000 37 #define SUNXI_TVE0_BASE 0x01c0a000 38 #define SUNXI_EMAC_BASE 0x01c0b000 39 #define SUNXI_LCD0_BASE 0x01c0C000 40 #define SUNXI_LCD1_BASE 0x01c0d000 41 #define SUNXI_VE_BASE 0x01c0e000 42 #define SUNXI_MMC0_BASE 0x01c0f000 43 #define SUNXI_MMC1_BASE 0x01c10000 44 #define SUNXI_MMC2_BASE 0x01c11000 45 #define SUNXI_MMC3_BASE 0x01c12000 46 #ifdef CONFIG_SUNXI_GEN_SUN4I 47 #define SUNXI_USB0_BASE 0x01c13000 48 #define SUNXI_USB1_BASE 0x01c14000 49 #endif 50 #define SUNXI_SS_BASE 0x01c15000 51 #if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) 52 #define SUNXI_HDMI_BASE 0x01c16000 53 #endif 54 #define SUNXI_SPI2_BASE 0x01c17000 55 #define SUNXI_SATA_BASE 0x01c18000 56 #ifdef CONFIG_SUNXI_GEN_SUN4I 57 #define SUNXI_PATA_BASE 0x01c19000 58 #define SUNXI_ACE_BASE 0x01c1a000 59 #define SUNXI_TVE1_BASE 0x01c1b000 60 #define SUNXI_USB2_BASE 0x01c1c000 61 #endif 62 #ifdef CONFIG_SUNXI_GEN_SUN6I 63 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) 64 #define SUNXI_USBPHY_BASE 0x01c19000 65 #define SUNXI_USB0_BASE 0x01c1a000 66 #define SUNXI_USB1_BASE 0x01c1b000 67 #define SUNXI_USB2_BASE 0x01c1c000 68 #define SUNXI_USB3_BASE 0x01c1d000 69 #else 70 #define SUNXI_USB0_BASE 0x01c19000 71 #define SUNXI_USB1_BASE 0x01c1a000 72 #define SUNXI_USB2_BASE 0x01c1b000 73 #endif 74 #endif 75 #define SUNXI_CSI1_BASE 0x01c1d000 76 #define SUNXI_TZASC_BASE 0x01c1e000 77 #define SUNXI_SPI3_BASE 0x01c1f000 78 79 #define SUNXI_CCM_BASE 0x01c20000 80 #define SUNXI_INTC_BASE 0x01c20400 81 #define SUNXI_PIO_BASE 0x01c20800 82 #define SUNXI_TIMER_BASE 0x01c20c00 83 #ifndef CONFIG_SUNXI_GEN_SUN6I 84 #define SUNXI_PWM_BASE 0x01c20e00 85 #endif 86 #define SUNXI_SPDIF_BASE 0x01c21000 87 #ifdef CONFIG_SUNXI_GEN_SUN6I 88 #define SUNXI_PWM_BASE 0x01c21400 89 #else 90 #define SUNXI_AC97_BASE 0x01c21400 91 #endif 92 #define SUNXI_IR0_BASE 0x01c21800 93 #define SUNXI_IR1_BASE 0x01c21c00 94 95 #define SUNXI_IIS_BASE 0x01c22400 96 #define SUNXI_LRADC_BASE 0x01c22800 97 #define SUNXI_AD_DA_BASE 0x01c22c00 98 #define SUNXI_KEYPAD_BASE 0x01c23000 99 #define SUNXI_TZPC_BASE 0x01c23400 100 101 #if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \ 102 defined(CONFIG_MACH_SUN50I) 103 /* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */ 104 #define SUNXI_SIDC_BASE 0x01c14000 105 #define SUNXI_SID_BASE 0x01c14200 106 #else 107 #define SUNXI_SID_BASE 0x01c23800 108 #endif 109 110 #define SUNXI_SJTAG_BASE 0x01c23c00 111 112 #define SUNXI_TP_BASE 0x01c25000 113 #define SUNXI_PMU_BASE 0x01c25400 114 115 #if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40 116 #define SUNXI_CPUCFG_BASE 0x01c25c00 117 #endif 118 119 #define SUNXI_UART0_BASE 0x01c28000 120 #define SUNXI_UART1_BASE 0x01c28400 121 #define SUNXI_UART2_BASE 0x01c28800 122 #define SUNXI_UART3_BASE 0x01c28c00 123 #define SUNXI_UART4_BASE 0x01c29000 124 #define SUNXI_UART5_BASE 0x01c29400 125 #define SUNXI_UART6_BASE 0x01c29800 126 #define SUNXI_UART7_BASE 0x01c29c00 127 #define SUNXI_PS2_0_BASE 0x01c2a000 128 #define SUNXI_PS2_1_BASE 0x01c2a400 129 130 #define SUNXI_TWI0_BASE 0x01c2ac00 131 #define SUNXI_TWI1_BASE 0x01c2b000 132 #define SUNXI_TWI2_BASE 0x01c2b400 133 #ifdef CONFIG_MACH_SUN6I 134 #define SUNXI_TWI3_BASE 0x01c0b800 135 #endif 136 #ifdef CONFIG_MACH_SUN7I 137 #define SUNXI_TWI3_BASE 0x01c2b800 138 #define SUNXI_TWI4_BASE 0x01c2c000 139 #endif 140 141 #define SUNXI_CAN_BASE 0x01c2bc00 142 143 #define SUNXI_SCR_BASE 0x01c2c400 144 145 #ifndef CONFIG_MACH_SUN6I 146 #define SUNXI_GPS_BASE 0x01c30000 147 #define SUNXI_MALI400_BASE 0x01c40000 148 #define SUNXI_GMAC_BASE 0x01c50000 149 #else 150 #define SUNXI_GMAC_BASE 0x01c30000 151 #endif 152 153 #define SUNXI_DRAM_COM_BASE 0x01c62000 154 #define SUNXI_DRAM_CTL0_BASE 0x01c63000 155 #define SUNXI_DRAM_CTL1_BASE 0x01c64000 156 #define SUNXI_DRAM_PHY0_BASE 0x01c65000 157 #define SUNXI_DRAM_PHY1_BASE 0x01c66000 158 159 #define SUNXI_GIC400_BASE 0x01c80000 160 161 /* module sram */ 162 #define SUNXI_SRAM_C_BASE 0x01d00000 163 164 #define SUNXI_DE_FE0_BASE 0x01e00000 165 #define SUNXI_DE_FE1_BASE 0x01e20000 166 #define SUNXI_DE_BE0_BASE 0x01e60000 167 #define SUNXI_DE_BE1_BASE 0x01e40000 168 #define SUNXI_MP_BASE 0x01e80000 169 #define SUNXI_AVG_BASE 0x01ea0000 170 171 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) 172 #define SUNXI_HDMI_BASE 0x01ee0000 173 #endif 174 175 #define SUNXI_RTC_BASE 0x01f00000 176 #define SUNXI_PRCM_BASE 0x01f01400 177 178 #if defined CONFIG_SUNXI_GEN_SUN6I && \ 179 !defined CONFIG_MACH_SUN8I_A83T && \ 180 !defined CONFIG_MACH_SUN8I_R40 181 #define SUNXI_CPUCFG_BASE 0x01f01c00 182 #endif 183 184 #define SUNXI_R_TWI_BASE 0x01f02400 185 #define SUNXI_R_UART_BASE 0x01f02800 186 #define SUNXI_R_PIO_BASE 0x01f02c00 187 #define SUN6I_P2WI_BASE 0x01f03400 188 #define SUNXI_RSB_BASE 0x01f03400 189 190 /* CoreSight Debug Module */ 191 #define SUNXI_CSDM_BASE 0x3f500000 192 193 #define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ 194 195 #define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ 196 197 #define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) 198 199 /* SS bonding ids used for cpu identification */ 200 #define SUNXI_SS_BOND_ID_A31 4 201 #define SUNXI_SS_BOND_ID_A31S 5 202 203 #ifndef __ASSEMBLY__ 204 void sunxi_board_init(void); 205 void sunxi_reset(void); 206 int sunxi_get_ss_bonding_id(void); 207 int sunxi_get_sid(unsigned int *sid); 208 #endif /* __ASSEMBLY__ */ 209 210 #endif /* _SUNXI_CPU_SUN4I_H */ 211