1 /* 2 * (C) Copyright 2007-2011 3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 4 * Tom Cubie <tangliang@allwinnertech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _SUNXI_CPU_SUN4I_H 10 #define _SUNXI_CPU_SUN4I_H 11 12 #define SUNXI_SRAM_A1_BASE 0x00000000 13 #define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ 14 15 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ 16 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ 17 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ 18 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ 19 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ 20 21 #define SUNXI_SRAMC_BASE 0x01c00000 22 #define SUNXI_DRAMC_BASE 0x01c01000 23 #define SUNXI_DMA_BASE 0x01c02000 24 #define SUNXI_NFC_BASE 0x01c03000 25 #define SUNXI_TS_BASE 0x01c04000 26 #define SUNXI_SPI0_BASE 0x01c05000 27 #define SUNXI_SPI1_BASE 0x01c06000 28 #define SUNXI_MS_BASE 0x01c07000 29 #define SUNXI_TVD_BASE 0x01c08000 30 #define SUNXI_CSI0_BASE 0x01c09000 31 #define SUNXI_TVE0_BASE 0x01c0a000 32 #define SUNXI_EMAC_BASE 0x01c0b000 33 #define SUNXI_LCD0_BASE 0x01c0C000 34 #define SUNXI_LCD1_BASE 0x01c0d000 35 #define SUNXI_VE_BASE 0x01c0e000 36 #define SUNXI_MMC0_BASE 0x01c0f000 37 #define SUNXI_MMC1_BASE 0x01c10000 38 #define SUNXI_MMC2_BASE 0x01c11000 39 #define SUNXI_MMC3_BASE 0x01c12000 40 #ifdef CONFIG_SUNXI_GEN_SUN4I 41 #define SUNXI_USB0_BASE 0x01c13000 42 #define SUNXI_USB1_BASE 0x01c14000 43 #endif 44 #define SUNXI_SS_BASE 0x01c15000 45 #define SUNXI_HDMI_BASE 0x01c16000 46 #define SUNXI_SPI2_BASE 0x01c17000 47 #define SUNXI_SATA_BASE 0x01c18000 48 #ifdef CONFIG_SUNXI_GEN_SUN4I 49 #define SUNXI_PATA_BASE 0x01c19000 50 #define SUNXI_ACE_BASE 0x01c1a000 51 #define SUNXI_TVE1_BASE 0x01c1b000 52 #define SUNXI_USB2_BASE 0x01c1c000 53 #endif 54 #ifdef CONFIG_SUNXI_GEN_SUN6I 55 #ifdef CONFIG_MACH_SUN8I_H3 56 #define SUNXI_USBPHY_BASE 0x01c19000 57 #define SUNXI_USB0_BASE 0x01c1a000 58 #define SUNXI_USB1_BASE 0x01c1b000 59 #define SUNXI_USB2_BASE 0x01c1c000 60 #define SUNXI_USB3_BASE 0x01c1d000 61 #else 62 #define SUNXI_USB0_BASE 0x01c19000 63 #define SUNXI_USB1_BASE 0x01c1a000 64 #define SUNXI_USB2_BASE 0x01c1b000 65 #endif 66 #endif 67 #define SUNXI_CSI1_BASE 0x01c1d000 68 #define SUNXI_TZASC_BASE 0x01c1e000 69 #define SUNXI_SPI3_BASE 0x01c1f000 70 71 #define SUNXI_CCM_BASE 0x01c20000 72 #define SUNXI_INTC_BASE 0x01c20400 73 #define SUNXI_PIO_BASE 0x01c20800 74 #define SUNXI_TIMER_BASE 0x01c20c00 75 #define SUNXI_SPDIF_BASE 0x01c21000 76 #define SUNXI_AC97_BASE 0x01c21400 77 #define SUNXI_IR0_BASE 0x01c21800 78 #define SUNXI_IR1_BASE 0x01c21c00 79 80 #define SUNXI_IIS_BASE 0x01c22400 81 #define SUNXI_LRADC_BASE 0x01c22800 82 #define SUNXI_AD_DA_BASE 0x01c22c00 83 #define SUNXI_KEYPAD_BASE 0x01c23000 84 #define SUNXI_TZPC_BASE 0x01c23400 85 86 #if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3) 87 /* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */ 88 #define SUNXI_SID_BASE 0x01c14200 89 #else 90 #define SUNXI_SID_BASE 0x01c23800 91 #endif 92 93 #define SUNXI_SJTAG_BASE 0x01c23c00 94 95 #define SUNXI_TP_BASE 0x01c25000 96 #define SUNXI_PMU_BASE 0x01c25400 97 #define SUN7I_CPUCFG_BASE 0x01c25c00 98 99 #define SUNXI_UART0_BASE 0x01c28000 100 #define SUNXI_UART1_BASE 0x01c28400 101 #define SUNXI_UART2_BASE 0x01c28800 102 #define SUNXI_UART3_BASE 0x01c28c00 103 #define SUNXI_UART4_BASE 0x01c29000 104 #define SUNXI_UART5_BASE 0x01c29400 105 #define SUNXI_UART6_BASE 0x01c29800 106 #define SUNXI_UART7_BASE 0x01c29c00 107 #define SUNXI_PS2_0_BASE 0x01c2a000 108 #define SUNXI_PS2_1_BASE 0x01c2a400 109 110 #define SUNXI_TWI0_BASE 0x01c2ac00 111 #define SUNXI_TWI1_BASE 0x01c2b000 112 #define SUNXI_TWI2_BASE 0x01c2b400 113 #ifdef CONFIG_MACH_SUN6I 114 #define SUNXI_TWI3_BASE 0x01c0b800 115 #endif 116 #ifdef CONFIG_MACH_SUN7I 117 #define SUNXI_TWI3_BASE 0x01c2b800 118 #define SUNXI_TWI4_BASE 0x01c2c000 119 #endif 120 121 #define SUNXI_CAN_BASE 0x01c2bc00 122 123 #define SUNXI_SCR_BASE 0x01c2c400 124 125 #ifndef CONFIG_MACH_SUN6I 126 #define SUNXI_GPS_BASE 0x01c30000 127 #define SUNXI_MALI400_BASE 0x01c40000 128 #define SUNXI_GMAC_BASE 0x01c50000 129 #else 130 #define SUNXI_GMAC_BASE 0x01c30000 131 #endif 132 133 #define SUNXI_DRAM_COM_BASE 0x01c62000 134 #define SUNXI_DRAM_CTL0_BASE 0x01c63000 135 #define SUNXI_DRAM_CTL1_BASE 0x01c64000 136 #define SUNXI_DRAM_PHY0_BASE 0x01c65000 137 #define SUNXI_DRAM_PHY1_BASE 0x01c66000 138 139 /* module sram */ 140 #define SUNXI_SRAM_C_BASE 0x01d00000 141 142 #define SUNXI_DE_FE0_BASE 0x01e00000 143 #define SUNXI_DE_FE1_BASE 0x01e20000 144 #define SUNXI_DE_BE0_BASE 0x01e60000 145 #define SUNXI_DE_BE1_BASE 0x01e40000 146 #define SUNXI_MP_BASE 0x01e80000 147 #define SUNXI_AVG_BASE 0x01ea0000 148 149 #define SUNXI_RTC_BASE 0x01f00000 150 #define SUNXI_PRCM_BASE 0x01f01400 151 #define SUN6I_CPUCFG_BASE 0x01f01c00 152 #define SUNXI_R_TWI_BASE 0x01f02400 153 #define SUNXI_R_UART_BASE 0x01f02800 154 #define SUNXI_R_PIO_BASE 0x01f02c00 155 #define SUN6I_P2WI_BASE 0x01f03400 156 #define SUNXI_RSB_BASE 0x01f03400 157 158 /* CoreSight Debug Module */ 159 #define SUNXI_CSDM_BASE 0x3f500000 160 161 #define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ 162 163 #define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ 164 165 #define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) 166 167 /* SS bonding ids used for cpu identification */ 168 #define SUNXI_SS_BOND_ID_A31 4 169 #define SUNXI_SS_BOND_ID_A31S 5 170 171 #ifndef __ASSEMBLY__ 172 void sunxi_board_init(void); 173 void sunxi_reset(void); 174 int sunxi_get_ss_bonding_id(void); 175 int sunxi_get_sid(unsigned int *sid); 176 #endif /* __ASSEMBLY__ */ 177 178 #endif /* _SUNXI_CPU_SUN4I_H */ 179