1 /* 2 * sun6i clock register definitions 3 * 4 * (C) Copyright 2007-2011 5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com> 6 * Tom Cubie <tangliang@allwinnertech.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _SUNXI_CLOCK_SUN6I_H 12 #define _SUNXI_CLOCK_SUN6I_H 13 14 struct sunxi_ccm_reg { 15 u32 pll1_cfg; /* 0x00 pll1 control */ 16 u32 reserved0; 17 u32 pll2_cfg; /* 0x08 pll2 control */ 18 u32 reserved1; 19 u32 pll3_cfg; /* 0x10 pll3 control */ 20 u32 reserved2; 21 u32 pll4_cfg; /* 0x18 pll4 control */ 22 u32 reserved3; 23 u32 pll5_cfg; /* 0x20 pll5 control */ 24 u32 reserved4; 25 u32 pll6_cfg; /* 0x28 pll6 control */ 26 u32 reserved5; 27 u32 pll7_cfg; /* 0x30 pll7 control */ 28 u32 reserved6; 29 u32 pll8_cfg; /* 0x38 pll8 control */ 30 u32 reserved7; 31 u32 mipi_pll_cfg; /* 0x40 MIPI pll control */ 32 u32 pll9_cfg; /* 0x44 pll9 control */ 33 u32 pll10_cfg; /* 0x48 pll10 control */ 34 u32 pll11_cfg; /* 0x4c pll11 (ddr1) control (A33 only) */ 35 u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ 36 u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ 37 u32 apb2_div; /* 0x58 APB2 divide ratio */ 38 u32 axi_gate; /* 0x5c axi module clock gating */ 39 u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ 40 u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ 41 u32 apb1_gate; /* 0x68 apb1 module clock gating */ 42 u32 apb2_gate; /* 0x6c apb2 module clock gating */ 43 u32 reserved9[4]; 44 u32 nand0_clk_cfg; /* 0x80 nand0 clock control */ 45 u32 nand1_clk_cfg; /* 0x84 nand1 clock control */ 46 u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ 47 u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ 48 u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ 49 u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ 50 u32 ts_clk_cfg; /* 0x98 transport stream clock control */ 51 u32 ss_clk_cfg; /* 0x9c security system clock control */ 52 u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ 53 u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ 54 u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */ 55 u32 spi3_clk_cfg; /* 0xac spi3 clock control */ 56 u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/ 57 u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ 58 u32 reserved10[2]; 59 u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ 60 u32 reserved11[2]; 61 u32 usb_clk_cfg; /* 0xcc USB clock control */ 62 u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */ 63 u32 reserved12[7]; 64 u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */ 65 u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ 66 u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */ 67 u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */ 68 u32 dram_clk_gate; /* 0x100 DRAM module gating */ 69 u32 be0_clk_cfg; /* 0x104 BE0 module clock */ 70 u32 be1_clk_cfg; /* 0x108 BE1 module clock */ 71 u32 fe0_clk_cfg; /* 0x10c FE0 module clock */ 72 u32 fe1_clk_cfg; /* 0x110 FE1 module clock */ 73 u32 mp_clk_cfg; /* 0x114 MP module clock */ 74 u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */ 75 u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */ 76 u32 reserved14[3]; 77 u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */ 78 u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */ 79 u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */ 80 u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */ 81 u32 ve_clk_cfg; /* 0x13c VE module clock */ 82 u32 adda_clk_cfg; /* 0x140 ADDA module clock */ 83 u32 avs_clk_cfg; /* 0x144 AVS module clock */ 84 u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/ 85 u32 reserved15; 86 u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ 87 u32 ps_clk_cfg; /* 0x154 PS module clock */ 88 u32 mtc_clk_cfg; /* 0x158 MTC module clock */ 89 u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */ 90 u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */ 91 u32 reserved16; 92 u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ 93 u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */ 94 u32 reserved17[4]; 95 u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */ 96 u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */ 97 u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */ 98 u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */ 99 u32 reserved18[4]; 100 u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ 101 u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ 102 u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */ 103 u32 reserved19[21]; 104 u32 pll_lock; /* 0x200 PLL Lock Time */ 105 u32 pll1_lock; /* 0x204 PLL1 Lock Time */ 106 u32 reserved20[6]; 107 u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */ 108 u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */ 109 u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */ 110 u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */ 111 u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */ 112 u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */ 113 u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */ 114 u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */ 115 u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */ 116 u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */ 117 u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */ 118 u32 reserved21[13]; 119 u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */ 120 u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */ 121 u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */ 122 u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */ 123 u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */ 124 u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */ 125 u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */ 126 u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */ 127 u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */ 128 u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */ 129 u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */ 130 u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */ 131 u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */ 132 u32 reserved22[3]; 133 u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ 134 u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ 135 u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ 136 u32 reserved23; 137 u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */ 138 u32 reserved24; 139 u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */ 140 u32 reserved25[5]; 141 u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */ 142 }; 143 144 /* apb2 bit field */ 145 #define APB2_CLK_SRC_LOSC (0x0 << 24) 146 #define APB2_CLK_SRC_OSC24M (0x1 << 24) 147 #define APB2_CLK_SRC_PLL6 (0x2 << 24) 148 #define APB2_CLK_SRC_MASK (0x3 << 24) 149 #define APB2_CLK_RATE_N_1 (0x0 << 16) 150 #define APB2_CLK_RATE_N_2 (0x1 << 16) 151 #define APB2_CLK_RATE_N_4 (0x2 << 16) 152 #define APB2_CLK_RATE_N_8 (0x3 << 16) 153 #define APB2_CLK_RATE_N_MASK (3 << 16) 154 #define APB2_CLK_RATE_M(m) (((m)-1) << 0) 155 #define APB2_CLK_RATE_M_MASK (0x1f << 0) 156 157 /* apb2 gate field */ 158 #define APB2_GATE_UART_SHIFT (16) 159 #define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) 160 #define APB2_GATE_TWI_SHIFT (0) 161 #define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) 162 163 /* cpu_axi_cfg bits */ 164 #define AXI_DIV_SHIFT 0 165 #define ATB_DIV_SHIFT 8 166 #define CPU_CLK_SRC_SHIFT 16 167 168 #define AXI_DIV_1 0 169 #define AXI_DIV_2 1 170 #define AXI_DIV_3 2 171 #define AXI_DIV_4 3 172 #define ATB_DIV_1 0 173 #define ATB_DIV_2 1 174 #define ATB_DIV_4 2 175 #define CPU_CLK_SRC_OSC24M 1 176 #define CPU_CLK_SRC_PLL1 2 177 178 #define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0) 179 #define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4) 180 #define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) 181 #define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16) 182 #define CCM_PLL1_CTRL_EN (0x1 << 31) 183 184 #define CCM_PLL3_CTRL_M_SHIFT 0 185 #define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT) 186 #define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0) 187 #define CCM_PLL3_CTRL_N_SHIFT 8 188 #define CCM_PLL3_CTRL_N_MASK (0x7f << CCM_PLL3_CTRL_N_SHIFT) 189 #define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8) 190 #define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24) 191 #define CCM_PLL3_CTRL_EN (0x1 << 31) 192 193 #define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0) 194 #define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4) 195 #define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) 196 #define CCM_PLL5_CTRL_UPD (0x1 << 20) 197 #define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24) 198 #define CCM_PLL5_CTRL_EN (0x1 << 31) 199 200 #define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */ 201 202 #define CCM_PLL6_CTRL_N_SHIFT 8 203 #define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) 204 #define CCM_PLL6_CTRL_K_SHIFT 4 205 #define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) 206 #define CCM_PLL6_CTRL_LOCK (1 << 28) 207 208 #define CCM_MIPI_PLL_CTRL_M_SHIFT 0 209 #define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT) 210 #define CCM_MIPI_PLL_CTRL_M(n) ((((n) - 1) & 0xf) << 0) 211 #define CCM_MIPI_PLL_CTRL_K_SHIFT 4 212 #define CCM_MIPI_PLL_CTRL_K_MASK (0x3 << CCM_MIPI_PLL_CTRL_K_SHIFT) 213 #define CCM_MIPI_PLL_CTRL_K(n) ((((n) - 1) & 0x3) << 4) 214 #define CCM_MIPI_PLL_CTRL_N_SHIFT 8 215 #define CCM_MIPI_PLL_CTRL_N_MASK (0xf << CCM_MIPI_PLL_CTRL_N_SHIFT) 216 #define CCM_MIPI_PLL_CTRL_N(n) ((((n) - 1) & 0xf) << 8) 217 #define CCM_MIPI_PLL_CTRL_LDO_EN (0x3 << 22) 218 #define CCM_MIPI_PLL_CTRL_EN (0x1 << 31) 219 220 #define CCM_PLL11_CTRL_N(n) ((((n) - 1) & 0x3f) << 8) 221 #define CCM_PLL11_CTRL_SIGMA_DELTA_EN (0x1 << 24) 222 #define CCM_PLL11_CTRL_UPD (0x1 << 30) 223 #define CCM_PLL11_CTRL_EN (0x1 << 31) 224 225 #define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ 226 227 #define AXI_GATE_OFFSET_DRAM 0 228 229 /* ahb_gate0 offsets */ 230 #define AHB_GATE_OFFSET_USB_OHCI1 30 231 #define AHB_GATE_OFFSET_USB_OHCI0 29 232 #define AHB_GATE_OFFSET_USB_EHCI1 27 233 #define AHB_GATE_OFFSET_USB_EHCI0 26 234 #define AHB_GATE_OFFSET_USB0 24 235 #define AHB_GATE_OFFSET_MCTL 14 236 #define AHB_GATE_OFFSET_GMAC 17 237 #define AHB_GATE_OFFSET_NAND0 13 238 #define AHB_GATE_OFFSET_NAND1 12 239 #define AHB_GATE_OFFSET_MMC3 11 240 #define AHB_GATE_OFFSET_MMC2 10 241 #define AHB_GATE_OFFSET_MMC1 9 242 #define AHB_GATE_OFFSET_MMC0 8 243 #define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) 244 #define AHB_GATE_OFFSET_DMA 6 245 #define AHB_GATE_OFFSET_SS 5 246 247 /* ahb_gate1 offsets */ 248 #define AHB_GATE_OFFSET_DRC0 25 249 #define AHB_GATE_OFFSET_DE_FE0 14 250 #define AHB_GATE_OFFSET_DE_BE0 12 251 #define AHB_GATE_OFFSET_HDMI 11 252 #define AHB_GATE_OFFSET_LCD1 5 253 #define AHB_GATE_OFFSET_LCD0 4 254 255 #define CCM_MMC_CTRL_M(x) ((x) - 1) 256 #define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) 257 #define CCM_MMC_CTRL_N(x) ((x) << 16) 258 #define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) 259 #define CCM_MMC_CTRL_OSCM24 (0x0 << 24) 260 #define CCM_MMC_CTRL_PLL6 (0x1 << 24) 261 #define CCM_MMC_CTRL_ENABLE (0x1 << 31) 262 263 #define CCM_USB_CTRL_PHY0_RST (0x1 << 0) 264 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1) 265 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2) 266 /* There is no global phy clk gate on sun6i, define as 0 */ 267 #define CCM_USB_CTRL_PHYGATE 0 268 #define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) 269 #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) 270 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) 271 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) 272 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) 273 274 #define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 275 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 276 #define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 277 #define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) 278 #define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) 279 #define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) 280 #define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) 281 282 #define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ 283 284 #define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0) 285 #define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0) 286 #define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) 287 #define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) 288 #define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20) 289 #define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20) 290 #define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20) 291 #define CCM_DRAMCLK_CFG_UPD (0x1 << 16) 292 #define CCM_DRAMCLK_CFG_RST (0x1 << 31) 293 294 #define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */ 295 #define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */ 296 #define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16) 297 298 #define CCM_MBUS_RESET_RESET (0x1 << 31) 299 300 #define CCM_DRAM_GATE_OFFSET_DE_FE0 24 301 #define CCM_DRAM_GATE_OFFSET_DE_FE1 25 302 #define CCM_DRAM_GATE_OFFSET_DE_BE0 26 303 #define CCM_DRAM_GATE_OFFSET_DE_BE1 27 304 305 #define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) 306 #define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) 307 #define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) 308 #define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) 309 #define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24) 310 /* No reset bit in ch0_clk_cfg (reset is controlled through ahb_reset1) */ 311 #define CCM_LCD_CH0_CTRL_RST 0 312 #define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) 313 314 #define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) 315 #define CCM_LCD_CH1_CTRL_HALF_SCLK1 0 /* no seperate sclk1 & 2 on sun6i */ 316 #define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) 317 #define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) 318 #define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) 319 #define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) 320 #define CCM_LCD_CH1_CTRL_GATE (0x1 << 31) 321 322 #define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) 323 #define CCM_HDMI_CTRL_PLL_MASK (3 << 24) 324 #define CCM_HDMI_CTRL_PLL3 (0 << 24) 325 #define CCM_HDMI_CTRL_PLL7 (1 << 24) 326 #define CCM_HDMI_CTRL_PLL3_2X (2 << 24) 327 #define CCM_HDMI_CTRL_PLL7_2X (3 << 24) 328 #define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30) 329 #define CCM_HDMI_CTRL_GATE (0x1 << 31) 330 331 #ifndef CONFIG_MACH_SUN8I 332 #define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ 333 #else 334 #define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */ 335 #endif 336 #define MBUS_CLK_GATE (0x1 << 31) 337 338 #define CCM_PLL5_PATTERN 0xd1303333 339 #define CCM_PLL11_PATTERN 0xf5860000 340 341 /* ahb_reset0 offsets */ 342 #define AHB_RESET_OFFSET_GMAC 17 343 #define AHB_RESET_OFFSET_MCTL 14 344 #define AHB_RESET_OFFSET_MMC3 11 345 #define AHB_RESET_OFFSET_MMC2 10 346 #define AHB_RESET_OFFSET_MMC1 9 347 #define AHB_RESET_OFFSET_MMC0 8 348 #define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) 349 #define AHB_RESET_OFFSET_SS 5 350 351 /* ahb_reset1 offsets */ 352 #define AHB_RESET_OFFSET_SAT 26 353 #define AHB_RESET_OFFSET_DRC0 25 354 #define AHB_RESET_OFFSET_DE_FE0 14 355 #define AHB_RESET_OFFSET_DE_BE0 12 356 #define AHB_RESET_OFFSET_HDMI 11 357 #define AHB_RESET_OFFSET_LCD1 5 358 #define AHB_RESET_OFFSET_LCD0 4 359 360 /* ahb_reset2 offsets */ 361 #define AHB_RESET_OFFSET_LVDS 0 362 363 /* apb2 reset */ 364 #define APB2_RESET_UART_SHIFT (16) 365 #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) 366 #define APB2_RESET_TWI_SHIFT (0) 367 #define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) 368 369 /* CCM bits common to all Display Engine (and IEP) clock ctrl regs */ 370 #define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) 371 #define CCM_DE_CTRL_PLL_MASK (0xf << 24) 372 #define CCM_DE_CTRL_PLL3 (0 << 24) 373 #define CCM_DE_CTRL_PLL7 (1 << 24) 374 #define CCM_DE_CTRL_PLL6_2X (2 << 24) 375 #define CCM_DE_CTRL_PLL8 (3 << 24) 376 #define CCM_DE_CTRL_PLL9 (4 << 24) 377 #define CCM_DE_CTRL_PLL10 (5 << 24) 378 #define CCM_DE_CTRL_GATE (1 << 31) 379 380 /* CCU security switch, H3 only */ 381 #define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2) 382 #define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1) 383 #define CCM_SEC_SWITCH_PLL_NONSEC (1 << 0) 384 385 #ifndef __ASSEMBLY__ 386 void clock_set_pll1(unsigned int hz); 387 void clock_set_pll3(unsigned int hz); 388 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable); 389 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable); 390 void clock_set_mipi_pll(unsigned int hz); 391 unsigned int clock_get_pll3(void); 392 unsigned int clock_get_pll6(void); 393 unsigned int clock_get_mipi_pll(void); 394 #endif 395 396 #endif /* _SUNXI_CLOCK_SUN6I_H */ 397