1 /*
2  * sun6i clock register definitions
3  *
4  * (C) Copyright 2007-2011
5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6  * Tom Cubie <tangliang@allwinnertech.com>
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef _SUNXI_CLOCK_SUN6I_H
12 #define _SUNXI_CLOCK_SUN6I_H
13 
14 struct sunxi_ccm_reg {
15 	u32 pll1_cfg;		/* 0x00 pll1 control */
16 	u32 reserved0;
17 	u32 pll2_cfg;		/* 0x08 pll2 control */
18 	u32 reserved1;
19 	u32 pll3_cfg;		/* 0x10 pll3 control */
20 	u32 reserved2;
21 	u32 pll4_cfg;		/* 0x18 pll4 control */
22 	u32 reserved3;
23 	u32 pll5_cfg;		/* 0x20 pll5 control */
24 	u32 reserved4;
25 	u32 pll6_cfg;		/* 0x28 pll6 control */
26 	u32 reserved5;
27 	u32 pll7_cfg;		/* 0x30 pll7 control */
28 	u32 reserved6;
29 	u32 pll8_cfg;		/* 0x38 pll8 control */
30 	u32 reserved7;
31 	u32 mipi_pll_cfg;	/* 0x40 MIPI pll control */
32 	u32 pll9_cfg;		/* 0x44 pll9 control */
33 	u32 pll10_cfg;		/* 0x48 pll10 control */
34 	u32 pll11_cfg;		/* 0x4c pll11 (ddr1) control (A33 only) */
35 	u32 cpu_axi_cfg;	/* 0x50 CPU/AXI divide ratio */
36 	u32 ahb1_apb1_div;	/* 0x54 AHB1/APB1 divide ratio */
37 	u32 apb2_div;		/* 0x58 APB2 divide ratio */
38 	u32 axi_gate;		/* 0x5c axi module clock gating */
39 	u32 ahb_gate0;		/* 0x60 ahb module clock gating 0 */
40 	u32 ahb_gate1;		/* 0x64 ahb module clock gating 1 */
41 	u32 apb1_gate;		/* 0x68 apb1 module clock gating */
42 	u32 apb2_gate;		/* 0x6c apb2 module clock gating */
43 	u32 bus_gate4;          /* 0x70 gate 4 module clock gating */
44 	u8 res3[0xc];
45 	u32 nand0_clk_cfg;	/* 0x80 nand0 clock control */
46 	u32 nand1_clk_cfg;	/* 0x84 nand1 clock control */
47 	u32 sd0_clk_cfg;	/* 0x88 sd0 clock control */
48 	u32 sd1_clk_cfg;	/* 0x8c sd1 clock control */
49 	u32 sd2_clk_cfg;	/* 0x90 sd2 clock control */
50 	u32 sd3_clk_cfg;	/* 0x94 sd3 clock control */
51 	u32 ts_clk_cfg;		/* 0x98 transport stream clock control */
52 	u32 ss_clk_cfg;		/* 0x9c security system clock control */
53 	u32 spi0_clk_cfg;	/* 0xa0 spi0 clock control */
54 	u32 spi1_clk_cfg;	/* 0xa4 spi1 clock control */
55 	u32 spi2_clk_cfg;	/* 0xa8 spi2 clock control */
56 	u32 spi3_clk_cfg;	/* 0xac spi3 clock control */
57 	u32 i2s0_clk_cfg;	/* 0xb0 I2S0 clock control*/
58 	u32 i2s1_clk_cfg;	/* 0xb4 I2S1 clock control */
59 	u32 reserved10[2];
60 	u32 spdif_clk_cfg;	/* 0xc0 SPDIF clock control */
61 	u32 reserved11[2];
62 	u32 usb_clk_cfg;	/* 0xcc USB clock control */
63 	u32 gmac_clk_cfg;	/* 0xd0 GMAC clock control */
64 	u32 reserved12[7];
65 	u32 mdfs_clk_cfg;	/* 0xf0 MDFS clock control */
66 	u32 dram_clk_cfg;	/* 0xf4 DRAM configuration clock control */
67 	u32 dram_pll_cfg;	/* 0xf8 PLL_DDR cfg register, A33 only */
68 	u32 mbus_reset;		/* 0xfc MBUS reset control, A33 only */
69 	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
70 	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
71 	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
72 	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
73 	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
74 	u32 mp_clk_cfg;		/* 0x114 MP module clock */
75 	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
76 	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
77 	u32 reserved14[3];
78 	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
79 	u32 lcd1_ch1_clk_cfg;	/* 0x130 LCD1 CH1 module clock */
80 	u32 csi0_clk_cfg;	/* 0x134 CSI0 module clock */
81 	u32 csi1_clk_cfg;	/* 0x138 CSI1 module clock */
82 	u32 ve_clk_cfg;		/* 0x13c VE module clock */
83 	u32 adda_clk_cfg;	/* 0x140 ADDA module clock */
84 	u32 avs_clk_cfg;	/* 0x144 AVS module clock */
85 	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
86 	u32 reserved15;
87 	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
88 	u32 ps_clk_cfg;		/* 0x154 PS module clock */
89 	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
90 	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
91 	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */
92 	u32 reserved16;
93 	u32 mipi_dsi_clk_cfg;	/* 0x168 MIPI DSI clock control */
94 	u32 mipi_csi_clk_cfg;	/* 0x16c MIPI CSI clock control */
95 	u32 reserved17[4];
96 	u32 iep_drc0_clk_cfg;	/* 0x180 IEP DRC0 module clock */
97 	u32 iep_drc1_clk_cfg;	/* 0x184 IEP DRC1 module clock */
98 	u32 iep_deu0_clk_cfg;	/* 0x188 IEP DEU0 module clock */
99 	u32 iep_deu1_clk_cfg;	/* 0x18c IEP DEU1 module clock */
100 	u32 reserved18[4];
101 	u32 gpu_core_clk_cfg;	/* 0x1a0 GPU core clock config */
102 	u32 gpu_mem_clk_cfg;	/* 0x1a4 GPU memory clock config */
103 	u32 gpu_hyd_clk_cfg;	/* 0x1a0 GPU HYD clock config */
104 	u32 reserved19[21];
105 	u32 pll_lock;		/* 0x200 PLL Lock Time */
106 	u32 pll1_lock;		/* 0x204 PLL1 Lock Time */
107 	u32 reserved20[6];
108 	u32 pll1_bias_cfg;	/* 0x220 PLL1 Bias config */
109 	u32 pll2_bias_cfg;	/* 0x224 PLL2 Bias config */
110 	u32 pll3_bias_cfg;	/* 0x228 PLL3 Bias config */
111 	u32 pll4_bias_cfg;	/* 0x22c PLL4 Bias config */
112 	u32 pll5_bias_cfg;	/* 0x230 PLL5 Bias config */
113 	u32 pll6_bias_cfg;	/* 0x234 PLL6 Bias config */
114 	u32 pll7_bias_cfg;	/* 0x238 PLL7 Bias config */
115 	u32 pll8_bias_cfg;	/* 0x23c PLL8 Bias config */
116 	u32 mipi_bias_cfg;	/* 0x240 MIPI Bias config */
117 	u32 pll9_bias_cfg;	/* 0x244 PLL9 Bias config */
118 	u32 pll10_bias_cfg;	/* 0x248 PLL10 Bias config */
119 	u32 reserved21[5];
120 	u32 pll5_tuning_cfg;	/* 0x260 PLL5 Tuning config */
121 	u32 reserved21_5[7];
122 	u32 pll1_pattern_cfg;	/* 0x280 PLL1 Pattern config */
123 	u32 pll2_pattern_cfg;	/* 0x284 PLL2 Pattern config */
124 	u32 pll3_pattern_cfg;	/* 0x288 PLL3 Pattern config */
125 	u32 pll4_pattern_cfg;	/* 0x28c PLL4 Pattern config */
126 	u32 pll5_pattern_cfg;	/* 0x290 PLL5 Pattern config */
127 	u32 pll6_pattern_cfg;	/* 0x294 PLL6 Pattern config */
128 	u32 pll7_pattern_cfg;	/* 0x298 PLL7 Pattern config */
129 	u32 pll8_pattern_cfg;	/* 0x29c PLL8 Pattern config */
130 	u32 mipi_pattern_cfg;	/* 0x2a0 MIPI Pattern config */
131 	u32 pll9_pattern_cfg;	/* 0x2a4 PLL9 Pattern config */
132 	u32 pll10_pattern_cfg;	/* 0x2a8 PLL10 Pattern config */
133 	u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */
134 	u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */
135 	u32 reserved22[3];
136 	u32 ahb_reset0_cfg;	/* 0x2c0 AHB1 Reset 0 config */
137 	u32 ahb_reset1_cfg;	/* 0x2c4 AHB1 Reset 1 config */
138 	u32 ahb_reset2_cfg;	/* 0x2c8 AHB1 Reset 2 config */
139 	u32 reserved23;
140 	u32 apb1_reset_cfg;	/* 0x2d0 APB1 Reset config */
141 	u32 reserved24;
142 	u32 apb2_reset_cfg;	/* 0x2d8 APB2 Reset config */
143 	u32 reserved25[5];
144 	u32 ccu_sec_switch;	/* 0x2f0 CCU Security Switch, H3 only */
145 };
146 
147 /* apb2 bit field */
148 #define APB2_CLK_SRC_LOSC		(0x0 << 24)
149 #define APB2_CLK_SRC_OSC24M		(0x1 << 24)
150 #define APB2_CLK_SRC_PLL6		(0x2 << 24)
151 #define APB2_CLK_SRC_MASK		(0x3 << 24)
152 #define APB2_CLK_RATE_N_1		(0x0 << 16)
153 #define APB2_CLK_RATE_N_2		(0x1 << 16)
154 #define APB2_CLK_RATE_N_4		(0x2 << 16)
155 #define APB2_CLK_RATE_N_8		(0x3 << 16)
156 #define APB2_CLK_RATE_N_MASK		(3 << 16)
157 #define APB2_CLK_RATE_M(m)		(((m)-1) << 0)
158 #define APB2_CLK_RATE_M_MASK            (0x1f << 0)
159 
160 /* apb2 gate field */
161 #define APB2_GATE_UART_SHIFT	(16)
162 #define APB2_GATE_UART_MASK		(0xff << APB2_GATE_UART_SHIFT)
163 #define APB2_GATE_TWI_SHIFT	(0)
164 #define APB2_GATE_TWI_MASK		(0xf << APB2_GATE_TWI_SHIFT)
165 
166 /* cpu_axi_cfg bits */
167 #define AXI_DIV_SHIFT			0
168 #define ATB_DIV_SHIFT			8
169 #define CPU_CLK_SRC_SHIFT		16
170 
171 #define AXI_DIV_1			0
172 #define AXI_DIV_2			1
173 #define AXI_DIV_3			2
174 #define AXI_DIV_4			3
175 #define ATB_DIV_1			0
176 #define ATB_DIV_2			1
177 #define ATB_DIV_4			2
178 #define CPU_CLK_SRC_OSC24M		1
179 #define CPU_CLK_SRC_PLL1		2
180 
181 #define CCM_PLL1_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
182 #define CCM_PLL1_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
183 #define CCM_PLL1_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
184 #define CCM_PLL1_CTRL_P(n)		(((n) & 0x3) << 16)
185 #define CCM_PLL1_CTRL_EN		(0x1 << 31)
186 
187 #define CCM_PLL3_CTRL_M_SHIFT		0
188 #define CCM_PLL3_CTRL_M_MASK		(0xf << CCM_PLL3_CTRL_M_SHIFT)
189 #define CCM_PLL3_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
190 #define CCM_PLL3_CTRL_N_SHIFT		8
191 #define CCM_PLL3_CTRL_N_MASK		(0x7f << CCM_PLL3_CTRL_N_SHIFT)
192 #define CCM_PLL3_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
193 #define CCM_PLL3_CTRL_INTEGER_MODE	(0x1 << 24)
194 #define CCM_PLL3_CTRL_EN		(0x1 << 31)
195 
196 #define CCM_PLL5_CTRL_M(n)		((((n) - 1) & 0x3) << 0)
197 #define CCM_PLL5_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
198 #define CCM_PLL5_CTRL_N(n)		((((n) - 1) & 0x1f) << 8)
199 #define CCM_PLL5_CTRL_UPD		(0x1 << 20)
200 #define CCM_PLL5_CTRL_SIGMA_DELTA_EN	(0x1 << 24)
201 #define CCM_PLL5_CTRL_EN		(0x1 << 31)
202 
203 #define PLL6_CFG_DEFAULT		0x90041811 /* 600 MHz */
204 
205 #define CCM_PLL6_CTRL_N_SHIFT		8
206 #define CCM_PLL6_CTRL_N_MASK		(0x1f << CCM_PLL6_CTRL_N_SHIFT)
207 #define CCM_PLL6_CTRL_K_SHIFT		4
208 #define CCM_PLL6_CTRL_K_MASK		(0x3 << CCM_PLL6_CTRL_K_SHIFT)
209 #define CCM_PLL6_CTRL_LOCK		(1 << 28)
210 
211 #define CCM_MIPI_PLL_CTRL_M_SHIFT	0
212 #define CCM_MIPI_PLL_CTRL_M_MASK	(0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)
213 #define CCM_MIPI_PLL_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
214 #define CCM_MIPI_PLL_CTRL_K_SHIFT	4
215 #define CCM_MIPI_PLL_CTRL_K_MASK	(0x3 << CCM_MIPI_PLL_CTRL_K_SHIFT)
216 #define CCM_MIPI_PLL_CTRL_K(n)		((((n) - 1) & 0x3) << 4)
217 #define CCM_MIPI_PLL_CTRL_N_SHIFT	8
218 #define CCM_MIPI_PLL_CTRL_N_MASK	(0xf << CCM_MIPI_PLL_CTRL_N_SHIFT)
219 #define CCM_MIPI_PLL_CTRL_N(n)		((((n) - 1) & 0xf) << 8)
220 #define CCM_MIPI_PLL_CTRL_LDO_EN	(0x3 << 22)
221 #define CCM_MIPI_PLL_CTRL_EN		(0x1 << 31)
222 
223 #define CCM_PLL11_CTRL_N(n)		((((n) - 1) & 0x3f) << 8)
224 #define CCM_PLL11_CTRL_SIGMA_DELTA_EN	(0x1 << 24)
225 #define CCM_PLL11_CTRL_UPD		(0x1 << 30)
226 #define CCM_PLL11_CTRL_EN		(0x1 << 31)
227 
228 #define CCM_PLL5_TUN_LOCK_TIME(x)	(((x) & 0x7) << 24)
229 #define CCM_PLL5_TUN_LOCK_TIME_MASK	CCM_PLL5_TUN_LOCK_TIME(0x7)
230 #define CCM_PLL5_TUN_INIT_FREQ(x)	(((x) & 0x7f) << 16)
231 #define CCM_PLL5_TUN_INIT_FREQ_MASK	CCM_PLL5_TUN_INIT_FREQ(0x7f)
232 
233 #if defined(CONFIG_MACH_SUN50I)
234 /* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
235 #define AHB1_ABP1_DIV_DEFAULT		0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
236 #else
237 #define AHB1_ABP1_DIV_DEFAULT		0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
238 #endif
239 
240 #define AXI_GATE_OFFSET_DRAM		0
241 
242 /* ahb_gate0 offsets */
243 #define AHB_GATE_OFFSET_USB_OHCI1	30
244 #define AHB_GATE_OFFSET_USB_OHCI0	29
245 #ifdef CONFIG_MACH_SUNXI_H3_H5
246 /*
247  * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
248  * them 0 - 2 like they were called on older SoCs.
249  */
250 #define AHB_GATE_OFFSET_USB_EHCI2	27
251 #define AHB_GATE_OFFSET_USB_EHCI1	26
252 #define AHB_GATE_OFFSET_USB_EHCI0	25
253 #else
254 #define AHB_GATE_OFFSET_USB_EHCI1	27
255 #define AHB_GATE_OFFSET_USB_EHCI0	26
256 #endif
257 #define AHB_GATE_OFFSET_USB0		24
258 #define AHB_GATE_OFFSET_MCTL		14
259 #define AHB_GATE_OFFSET_GMAC		17
260 #define AHB_GATE_OFFSET_NAND0		13
261 #define AHB_GATE_OFFSET_NAND1		12
262 #define AHB_GATE_OFFSET_MMC3		11
263 #define AHB_GATE_OFFSET_MMC2		10
264 #define AHB_GATE_OFFSET_MMC1		9
265 #define AHB_GATE_OFFSET_MMC0		8
266 #define AHB_GATE_OFFSET_MMC(n)		(AHB_GATE_OFFSET_MMC0 + (n))
267 #define AHB_GATE_OFFSET_DMA		6
268 #define AHB_GATE_OFFSET_SS		5
269 
270 /* ahb_gate1 offsets */
271 #define AHB_GATE_OFFSET_DRC0		25
272 #define AHB_GATE_OFFSET_DE_FE0		14
273 #define AHB_GATE_OFFSET_DE_BE0		12
274 #define AHB_GATE_OFFSET_HDMI		11
275 #define AHB_GATE_OFFSET_LCD1		5
276 #define AHB_GATE_OFFSET_LCD0		4
277 
278 #define CCM_MMC_CTRL_M(x)		((x) - 1)
279 #define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
280 #define CCM_MMC_CTRL_N(x)		((x) << 16)
281 #define CCM_MMC_CTRL_SCLK_DLY(x)	((x) << 20)
282 #define CCM_MMC_CTRL_OSCM24		(0x0 << 24)
283 #define CCM_MMC_CTRL_PLL6		(0x1 << 24)
284 #define CCM_MMC_CTRL_ENABLE		(0x1 << 31)
285 
286 #define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
287 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
288 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
289 #define CCM_USB_CTRL_PHY3_RST (0x1 << 3)
290 /* There is no global phy clk gate on sun6i, define as 0 */
291 #define CCM_USB_CTRL_PHYGATE 0
292 #define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
293 #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
294 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
295 #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
296 #ifdef CONFIG_MACH_SUNXI_H3_H5
297 /*
298  * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
299  * them 0 - 2 like they were called on older SoCs.
300  */
301 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
302 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
303 #define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
304 #else
305 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
306 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
307 #endif
308 
309 #define CCM_GMAC_CTRL_TX_CLK_SRC_MII	0x0
310 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
311 #define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
312 #define CCM_GMAC_CTRL_GPIT_MII		(0x0 << 2)
313 #define CCM_GMAC_CTRL_GPIT_RGMII	(0x1 << 2)
314 #define CCM_GMAC_CTRL_RX_CLK_DELAY(x)	((x) << 5)
315 #define CCM_GMAC_CTRL_TX_CLK_DELAY(x)	((x) << 10)
316 
317 #define MDFS_CLK_DEFAULT		0x81000002 /* PLL6 / 3 */
318 
319 #define CCM_DRAMCLK_CFG_DIV(x)		((x - 1) << 0)
320 #define CCM_DRAMCLK_CFG_DIV_MASK	(0xf << 0)
321 #define CCM_DRAMCLK_CFG_DIV0(x)		((x - 1) << 8)
322 #define CCM_DRAMCLK_CFG_DIV0_MASK	(0xf << 8)
323 #define CCM_DRAMCLK_CFG_SRC_PLL5	(0x0 << 20)
324 #define CCM_DRAMCLK_CFG_SRC_PLL6x2	(0x1 << 20)
325 #define CCM_DRAMCLK_CFG_SRC_PLL11	(0x1 << 20) /* A64 only */
326 #define CCM_DRAMCLK_CFG_SRC_MASK	(0x3 << 20)
327 #define CCM_DRAMCLK_CFG_UPD		(0x1 << 16)
328 #define CCM_DRAMCLK_CFG_RST		(0x1 << 31)
329 
330 #define CCM_DRAMPLL_CFG_SRC_PLL5	(0x0 << 16) /* Select PLL5 (DDR0) */
331 #define CCM_DRAMPLL_CFG_SRC_PLL11	(0x1 << 16) /* Select PLL11 (DDR1) */
332 #define CCM_DRAMPLL_CFG_SRC_MASK	(0x1 << 16)
333 
334 #define CCM_MBUS_RESET_RESET		(0x1 << 31)
335 
336 #define CCM_DRAM_GATE_OFFSET_DE_FE0	24
337 #define CCM_DRAM_GATE_OFFSET_DE_FE1	25
338 #define CCM_DRAM_GATE_OFFSET_DE_BE0	26
339 #define CCM_DRAM_GATE_OFFSET_DE_BE1	27
340 
341 #define CCM_LCD_CH0_CTRL_PLL3		(0 << 24)
342 #define CCM_LCD_CH0_CTRL_PLL7		(1 << 24)
343 #define CCM_LCD_CH0_CTRL_PLL3_2X	(2 << 24)
344 #define CCM_LCD_CH0_CTRL_PLL7_2X	(3 << 24)
345 #define CCM_LCD_CH0_CTRL_MIPI_PLL	(4 << 24)
346 /* No reset bit in ch0_clk_cfg (reset is controlled through ahb_reset1) */
347 #define CCM_LCD_CH0_CTRL_RST		0
348 #define CCM_LCD_CH0_CTRL_GATE		(0x1 << 31)
349 
350 #define CCM_LCD_CH1_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
351 #define CCM_LCD_CH1_CTRL_HALF_SCLK1	0 /* no seperate sclk1 & 2 on sun6i */
352 #define CCM_LCD_CH1_CTRL_PLL3		(0 << 24)
353 #define CCM_LCD_CH1_CTRL_PLL7		(1 << 24)
354 #define CCM_LCD_CH1_CTRL_PLL3_2X	(2 << 24)
355 #define CCM_LCD_CH1_CTRL_PLL7_2X	(3 << 24)
356 #define CCM_LCD_CH1_CTRL_GATE		(0x1 << 31)
357 
358 #define CCM_HDMI_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
359 #define CCM_HDMI_CTRL_PLL_MASK		(3 << 24)
360 #define CCM_HDMI_CTRL_PLL3		(0 << 24)
361 #define CCM_HDMI_CTRL_PLL7		(1 << 24)
362 #define CCM_HDMI_CTRL_PLL3_2X		(2 << 24)
363 #define CCM_HDMI_CTRL_PLL7_2X		(3 << 24)
364 #define CCM_HDMI_CTRL_DDC_GATE		(0x1 << 30)
365 #define CCM_HDMI_CTRL_GATE		(0x1 << 31)
366 
367 #if defined(CONFIG_MACH_SUN50I)
368 #define MBUS_CLK_DEFAULT		0x81000002 /* PLL6x2 / 3 */
369 #elif defined(CONFIG_MACH_SUN8I)
370 #define MBUS_CLK_DEFAULT		0x81000003 /* PLL6 / 4 */
371 #else
372 #define MBUS_CLK_DEFAULT		0x81000001 /* PLL6 / 2 */
373 #endif
374 #define MBUS_CLK_GATE			(0x1 << 31)
375 
376 #define CCM_PLL5_PATTERN		0xd1303333
377 #define CCM_PLL11_PATTERN		0xf5860000
378 
379 /* ahb_reset0 offsets */
380 #define AHB_RESET_OFFSET_GMAC		17
381 #define AHB_RESET_OFFSET_MCTL		14
382 #define AHB_RESET_OFFSET_MMC3		11
383 #define AHB_RESET_OFFSET_MMC2		10
384 #define AHB_RESET_OFFSET_MMC1		9
385 #define AHB_RESET_OFFSET_MMC0		8
386 #define AHB_RESET_OFFSET_MMC(n)		(AHB_RESET_OFFSET_MMC0 + (n))
387 #define AHB_RESET_OFFSET_SS		5
388 
389 /* ahb_reset1 offsets */
390 #define AHB_RESET_OFFSET_SAT		26
391 #define AHB_RESET_OFFSET_DRC0		25
392 #define AHB_RESET_OFFSET_DE_FE0		14
393 #define AHB_RESET_OFFSET_DE_BE0		12
394 #define AHB_RESET_OFFSET_HDMI		11
395 #define AHB_RESET_OFFSET_LCD1		5
396 #define AHB_RESET_OFFSET_LCD0		4
397 
398 /* ahb_reset2 offsets */
399 #define AHB_RESET_OFFSET_EPHY		2
400 #define AHB_RESET_OFFSET_LVDS		0
401 
402 /* apb2 reset */
403 #define APB2_RESET_UART_SHIFT		(16)
404 #define APB2_RESET_UART_MASK		(0xff << APB2_RESET_UART_SHIFT)
405 #define APB2_RESET_TWI_SHIFT		(0)
406 #define APB2_RESET_TWI_MASK		(0xf << APB2_RESET_TWI_SHIFT)
407 
408 /* CCM bits common to all Display Engine (and IEP) clock ctrl regs */
409 #define CCM_DE_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
410 #define CCM_DE_CTRL_PLL_MASK		(0xf << 24)
411 #define CCM_DE_CTRL_PLL3		(0 << 24)
412 #define CCM_DE_CTRL_PLL7		(1 << 24)
413 #define CCM_DE_CTRL_PLL6_2X		(2 << 24)
414 #define CCM_DE_CTRL_PLL8		(3 << 24)
415 #define CCM_DE_CTRL_PLL9		(4 << 24)
416 #define CCM_DE_CTRL_PLL10		(5 << 24)
417 #define CCM_DE_CTRL_GATE		(1 << 31)
418 
419 /* CCU security switch, H3 only */
420 #define CCM_SEC_SWITCH_MBUS_NONSEC	(1 << 2)
421 #define CCM_SEC_SWITCH_BUS_NONSEC	(1 << 1)
422 #define CCM_SEC_SWITCH_PLL_NONSEC	(1 << 0)
423 
424 #ifndef __ASSEMBLY__
425 void clock_set_pll1(unsigned int hz);
426 void clock_set_pll3(unsigned int hz);
427 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
428 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
429 void clock_set_mipi_pll(unsigned int hz);
430 unsigned int clock_get_pll3(void);
431 unsigned int clock_get_pll6(void);
432 unsigned int clock_get_mipi_pll(void);
433 #endif
434 
435 #endif /* _SUNXI_CLOCK_SUN6I_H */
436