1 /* 2 * Allwinner H6 clock register definitions 3 * 4 * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _SUNXI_CLOCK_SUN50I_H6_H 10 #define _SUNXI_CLOCK_SUN50I_H6_H 11 12 struct sunxi_ccm_reg { 13 u32 pll1_cfg; /* 0x000 pll1 (cpux) control */ 14 u8 reserved_0x004[12]; 15 u32 pll5_cfg; /* 0x010 pll5 (ddr) control */ 16 u8 reserved_0x014[12]; 17 u32 pll6_cfg; /* 0x020 pll6 (periph0) control */ 18 u8 reserved_0x020[4]; 19 u32 pll_periph1_cfg; /* 0x028 pll periph1 control */ 20 u8 reserved_0x028[4]; 21 u32 pll7_cfg; /* 0x030 pll7 (gpu) control */ 22 u8 reserved_0x034[12]; 23 u32 pll3_cfg; /* 0x040 pll3 (video0) control */ 24 u8 reserved_0x044[4]; 25 u32 pll_video1_cfg; /* 0x048 pll video1 control */ 26 u8 reserved_0x04c[12]; 27 u32 pll4_cfg; /* 0x058 pll4 (ve) control */ 28 u8 reserved_0x05c[4]; 29 u32 pll10_cfg; /* 0x060 pll10 (de) control */ 30 u8 reserved_0x064[12]; 31 u32 pll9_cfg; /* 0x070 pll9 (hsic) control */ 32 u8 reserved_0x074[4]; 33 u32 pll2_cfg; /* 0x078 pll2 (audio) control */ 34 u8 reserved_0x07c[148]; 35 u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */ 36 u8 reserved_0x114[20]; 37 u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */ 38 u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */ 39 u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */ 40 u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */ 41 u8 reserved_0x138[8]; 42 u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */ 43 u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */ 44 u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */ 45 u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */ 46 u8 reserved_0x150[8]; 47 u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */ 48 u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */ 49 u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */ 50 u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */ 51 u8 reserved_0x168[8]; 52 u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */ 53 u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */ 54 u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */ 55 u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */ 56 u8 reserved_0x180[384]; 57 u32 pll1_bias; /* 0x300 pll1 (cpux) bias */ 58 u8 reserved_0x304[12]; 59 u32 pll5_bias; /* 0x310 pll5 (ddr) bias */ 60 u8 reserved_0x314[12]; 61 u32 pll6_bias; /* 0x320 pll6 (periph0) bias */ 62 u8 reserved_0x324[4]; 63 u32 pll_periph1_bias; /* 0x328 pll periph1 bias */ 64 u8 reserved_0x32c[4]; 65 u32 pll7_bias; /* 0x330 pll7 (gpu) bias */ 66 u8 reserved_0x334[12]; 67 u32 pll3_bias; /* 0x340 pll3 (video0) bias */ 68 u8 reserved_0x344[4]; 69 u32 pll_video1_bias; /* 0x348 pll video1 bias */ 70 u8 reserved_0x34c[12]; 71 u32 pll4_bias; /* 0x358 pll4 (ve) bias */ 72 u8 reserved_0x35c[4]; 73 u32 pll10_bias; /* 0x360 pll10 (de) bias */ 74 u8 reserved_0x364[12]; 75 u32 pll9_bias; /* 0x370 pll9 (hsic) bias */ 76 u8 reserved_0x374[4]; 77 u32 pll2_bias; /* 0x378 pll2 (audio) bias */ 78 u8 reserved_0x37c[132]; 79 u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */ 80 u8 reserved_0x404[252]; 81 u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/ 82 u8 reserved_0x504[12]; 83 u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */ 84 u8 reserved_0x514[8]; 85 u32 ahb3_cfg; /* 0x51c AHB3 clock control */ 86 u32 apb1_cfg; /* 0x520 APB1 clock control */ 87 u32 apb2_cfg; /* 0x524 APB2 clock control */ 88 u8 reserved_0x528[24]; 89 u32 mbus_cfg; /* 0x540 MBUS clock control */ 90 u8 reserved_0x544[188]; 91 u32 de_clk_cfg; /* 0x600 DE clock control */ 92 u8 reserved_0x604[8]; 93 u32 de_gate_reset; /* 0x60c DE gate/reset control */ 94 u8 reserved_0x610[16]; 95 u32 di_clk_cfg; /* 0x620 DI clock control */ 96 u8 reserved_0x024[8]; 97 u32 di_gate_reset; /* 0x62c DI gate/reset control */ 98 u8 reserved_0x630[64]; 99 u32 gpu_clk_cfg; /* 0x670 GPU clock control */ 100 u8 reserved_0x674[8]; 101 u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */ 102 u32 ce_clk_cfg; /* 0x680 CE clock control */ 103 u8 reserved_0x684[8]; 104 u32 ce_gate_reset; /* 0x68c CE gate/reset control */ 105 u32 ve_clk_cfg; /* 0x690 VE clock control */ 106 u8 reserved_0x694[8]; 107 u32 ve_gate_reset; /* 0x69c VE gate/reset control */ 108 u8 reserved_0x6a0[16]; 109 u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */ 110 u8 reserved_0x6b4[8]; 111 u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */ 112 u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */ 113 u8 reserved_0x6c4[8]; 114 u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */ 115 u8 reserved_0x6d0[60]; 116 u32 dma_gate_reset; /* 0x70c DMA gate/reset control */ 117 u8 reserved_0x710[12]; 118 u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */ 119 u8 reserved_0x720[12]; 120 u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */ 121 u8 reserved_0x730[12]; 122 u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */ 123 u32 avs_gate_reset; /* 0x740 AVS gate/reset control */ 124 u8 reserved_0x744[72]; 125 u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */ 126 u8 reserved_0x790[12]; 127 u32 psi_gate_reset; /* 0x79c PSI gate/reset control */ 128 u8 reserved_0x7a0[12]; 129 u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */ 130 u8 reserved_0x7b0[12]; 131 u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */ 132 u8 reserved_0x7c0[64]; 133 u32 dram_clk_cfg; /* 0x800 DRAM clock control */ 134 u32 mbus_gate; /* 0x804 MBUS gate control */ 135 u8 reserved_0x808[4]; 136 u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */ 137 u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */ 138 u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */ 139 u8 reserved_0x818[20]; 140 u32 nand_gate_reset; /* 0x82c NAND gate/reset control */ 141 u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */ 142 u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */ 143 u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */ 144 u8 reserved_0x83c[16]; 145 u32 sd_gate_reset; /* 0x84c MMC gate/reset control */ 146 u8 reserved_0x850[188]; 147 u32 uart_gate_reset; /* 0x90c UART gate/reset control */ 148 u8 reserved_0x910[12]; 149 u32 twi_gate_reset; /* 0x91c I2C gate/reset control */ 150 u8 reserved_0x920[28]; 151 u32 scr_gate_reset; /* 0x93c SCR gate/reset control */ 152 u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */ 153 u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */ 154 u8 reserved_0x948[36]; 155 u32 spi_gate_reset; /* 0x96c SPI gate/reset control */ 156 u8 reserved_0x970[12]; 157 u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */ 158 u8 reserved_0x980[48]; 159 u32 ts_clk_cfg; /* 0x9b0 TS clock control */ 160 u8 reserved_0x9b4[8]; 161 u32 ts_gate_reset; /* 0x9bc TS gate/reset control */ 162 u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */ 163 u8 reserved_0x9c4[8]; 164 u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */ 165 u8 reserved_0x9d0[44]; 166 u32 ths_gate_reset; /* 0x9fc THS gate/reset control */ 167 u8 reserved_0xa00[12]; 168 u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */ 169 u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */ 170 u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */ 171 u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */ 172 u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */ 173 u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */ 174 u8 reserved_0xa24[8]; 175 u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */ 176 u8 reserved_0xa30[16]; 177 u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */ 178 u8 reserved_0xa44[8]; 179 u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */ 180 u8 reserved_0xa50[16]; 181 u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */ 182 u8 reserved_0xa64[8]; 183 u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */ 184 u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */ 185 u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */ 186 u8 reserved_0xa78[4]; 187 u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */ 188 u8 reserved_0xa80[12]; 189 u32 usb_gate_reset; /* 0xa8c USB gate/reset control */ 190 u8 reserved_0xa90[32]; 191 u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */ 192 u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */ 193 u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */ 194 u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */ 195 u8 reserved_0xac0[64]; 196 u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */ 197 u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */ 198 u8 reserved_0xb08[8]; 199 u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */ 200 u8 reserved_0xb14[8]; 201 u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */ 202 u8 reserved_0xb20[60]; 203 u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */ 204 u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */ 205 u8 reserved_0xb64[24]; 206 u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */ 207 u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */ 208 u8 reserved_0xb84[24]; 209 u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */ 210 u8 reserved_0xba0[96]; 211 u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */ 212 u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */ 213 u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */ 214 u8 reserved_0xc0c[32]; 215 u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */ 216 u8 reserved_0xc30[16]; 217 u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */ 218 u8 reserved_0xc44[8]; 219 u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */ 220 u8 reserved_0xc50[688]; 221 u32 ccu_sec_switch; /* 0xf00 CCU security switch */ 222 u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */ 223 }; 224 225 /* pll1 bit field */ 226 #define CCM_PLL1_CTRL_EN BIT(31) 227 #define CCM_PLL1_LOCK_EN BIT(29) 228 #define CCM_PLL1_LOCK BIT(28) 229 #define CCM_PLL1_CLOCK_TIME_2 (2 << 24) 230 #define CCM_PLL1_CTRL_P(p) ((p) << 16) 231 #define CCM_PLL1_CTRL_N(n) ((n) << 8) 232 233 /* pll5 bit field */ 234 #define CCM_PLL5_CTRL_EN BIT(31) 235 #define CCM_PLL5_LOCK_EN BIT(29) 236 #define CCM_PLL5_LOCK BIT(28) 237 #define CCM_PLL5_CTRL_N(n) ((n) << 8) 238 #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) 239 #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) 240 241 /* pll6 bit field */ 242 #define CCM_PLL6_CTRL_EN BIT(31) 243 #define CCM_PLL6_LOCK_EN BIT(29) 244 #define CCM_PLL6_LOCK BIT(28) 245 #define CCM_PLL6_CTRL_N_SHIFT 8 246 #define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT) 247 #define CCM_PLL6_CTRL_DIV1_SHIFT 0 248 #define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT) 249 #define CCM_PLL6_CTRL_DIV2_SHIFT 1 250 #define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT) 251 #define CCM_PLL6_DEFAULT 0xa0006300 252 253 /* cpu_axi bit field*/ 254 #define CCM_CPU_AXI_MUX_MASK (0x3 << 24) 255 #define CCM_CPU_AXI_MUX_OSC24M (0x0 << 24) 256 #define CCM_CPU_AXI_MUX_PLL_CPUX (0x3 << 24) 257 #define CCM_CPU_AXI_APB_MASK 0x300 258 #define CCM_CPU_AXI_AXI_MASK 0x3 259 #define CCM_CPU_AXI_DEFAULT_FACTORS 0x301 260 261 /* psi_ahb1_ahb2 bit field */ 262 #define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000102 263 264 /* ahb3 bit field */ 265 #define CCM_AHB3_DEFAULT 0x03000002 266 267 /* apb1 bit field */ 268 #define CCM_APB1_DEFAULT 0x03000102 269 270 /* apb2 bit field */ 271 #define APB2_CLK_SRC_OSC24M (0x0 << 24) 272 #define APB2_CLK_SRC_OSC32K (0x1 << 24) 273 #define APB2_CLK_SRC_PSI (0x2 << 24) 274 #define APB2_CLK_SRC_PLL6 (0x3 << 24) 275 #define APB2_CLK_SRC_MASK (0x3 << 24) 276 #define APB2_CLK_RATE_N_1 (0x0 << 8) 277 #define APB2_CLK_RATE_N_2 (0x1 << 8) 278 #define APB2_CLK_RATE_N_4 (0x2 << 8) 279 #define APB2_CLK_RATE_N_8 (0x3 << 8) 280 #define APB2_CLK_RATE_N_MASK (3 << 8) 281 #define APB2_CLK_RATE_M(m) (((m)-1) << 0) 282 #define APB2_CLK_RATE_M_MASK (3 << 0) 283 284 /* MBUS clock bit field */ 285 #define MBUS_ENABLE BIT(31) 286 #define MBUS_RESET BIT(30) 287 #define MBUS_CLK_SRC_MASK GENMASK(25, 24) 288 #define MBUS_CLK_SRC_OSCM24 (0 << 24) 289 #define MBUS_CLK_SRC_PLL6X2 (1 << 24) 290 #define MBUS_CLK_SRC_PLL5 (2 << 24) 291 #define MBUS_CLK_SRC_PLL6X4 (3 << 24) 292 #define MBUS_CLK_M(m) (((m)-1) << 0) 293 294 /* Module gate/reset shift*/ 295 #define RESET_SHIFT (16) 296 297 /* DRAM clock bit field */ 298 #define DRAM_MOD_RESET BIT(30) 299 #define DRAM_CLK_UPDATE BIT(27) 300 #define DRAM_CLK_SRC_MASK GENMASK(25, 24) 301 #define DRAM_CLK_SRC_PLL5 (0 << 24) 302 #define DRAM_CLK_M(m) (((m)-1) << 0) 303 304 /* MMC clock bit field */ 305 #define CCM_MMC_CTRL_M(x) ((x) - 1) 306 #define CCM_MMC_CTRL_N(x) ((x) << 8) 307 #define CCM_MMC_CTRL_OSCM24 (0x0 << 24) 308 #define CCM_MMC_CTRL_PLL6X2 (0x1 << 24) 309 #define CCM_MMC_CTRL_PLL_PERIPH2X2 (0x2 << 24) 310 #define CCM_MMC_CTRL_ENABLE (0x1 << 31) 311 /* H6 doesn't have these delays */ 312 #define CCM_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0) 313 #define CCM_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0) 314 315 #ifndef __ASSEMBLY__ 316 void clock_set_pll1(unsigned int hz); 317 unsigned int clock_get_pll6(void); 318 #endif 319 320 #endif /* _SUNXI_CLOCK_SUN50I_H6_H */ 321