1 /*
2  * (C) Copyright 2014
3  * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _STV0991_CGU_H
9 #define _STV0991_CGU_H
10 
11 struct stv0991_cgu_regs {
12 	u32 cpu_freq;		/* offset 0x0 */
13 	u32 icn2_freq;		/* offset 0x4 */
14 	u32 dma_freq;		/* offset 0x8 */
15 	u32 isp_freq;		/* offset 0xc */
16 	u32 h264_freq;		/* offset 0x10 */
17 	u32 osif_freq;		/* offset 0x14 */
18 	u32 ren_freq;		/* offset 0x18 */
19 	u32 tim_freq;		/* offset 0x1c */
20 	u32 sai_freq;		/* offset 0x20 */
21 	u32 eth_freq;		/* offset 0x24 */
22 	u32 i2c_freq;		/* offset 0x28 */
23 	u32 spi_freq;		/* offset 0x2c */
24 	u32 uart_freq;		/* offset 0x30 */
25 	u32 qspi_freq;		/* offset 0x34 */
26 	u32 sdio_freq;		/* offset 0x38 */
27 	u32 usi_freq;		/* offset 0x3c */
28 	u32 can_line_freq;	/* offset 0x40 */
29 	u32 debug_freq;		/* offset 0x44 */
30 	u32 trace_freq;		/* offset 0x48 */
31 	u32 stm_freq;		/* offset 0x4c */
32 	u32 eth_ctrl;		/* offset 0x50 */
33 	u32 reserved[3];	/* offset 0x54 */
34 	u32 osc_ctrl;		/* offset 0x60 */
35 	u32 pll1_ctrl;		/* offset 0x64 */
36 	u32 pll1_freq;		/* offset 0x68 */
37 	u32 pll1_fract;		/* offset 0x6c */
38 	u32 pll1_spread;	/* offset 0x70 */
39 	u32 pll1_status;	/* offset 0x74 */
40 	u32 pll2_ctrl;		/* offset 0x78 */
41 	u32 pll2_freq;		/* offset 0x7c */
42 	u32 pll2_fract;		/* offset 0x80 */
43 	u32 pll2_spread;	/* offset 0x84 */
44 	u32 pll2_status;	/* offset 0x88 */
45 	u32 cgu_enable_1;	/* offset 0x8c */
46 	u32 cgu_enable_2;	/* offset 0x90 */
47 	u32 cgu_isp_pulse;	/* offset 0x94 */
48 	u32 cgu_h264_pulse;	/* offset 0x98 */
49 	u32 cgu_osif_pulse;	/* offset 0x9c */
50 	u32 cgu_ren_pulse;	/* offset 0xa0 */
51 
52 };
53 
54 /* CGU Timer */
55 #define CLK_TMR_OSC			0
56 #define CLK_TMR_MCLK			1
57 #define CLK_TMR_PLL1			2
58 #define CLK_TMR_PLL2			3
59 #define MDIV_SHIFT_TMR			3
60 #define DIV_SHIFT_TMR			6
61 
62 #define TIMER1_CLK_CFG			(0 << DIV_SHIFT_TMR \
63 					| 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)
64 
65 /* Clock Enable/Disable */
66 
67 #define TIMER1_CLK_EN			(1 << 15)
68 
69 /* CGU Uart config */
70 #define CLK_UART_MCLK			0
71 #define CLK_UART_PLL1			1
72 #define CLK_UART_PLL2			2
73 
74 #define MDIV_SHIFT_UART			3
75 #define DIV_SHIFT_UART			6
76 
77 #define UART_CLK_CFG			(4 << DIV_SHIFT_UART \
78 					| 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
79 
80 /* CGU Ethernet clock config */
81 #define CLK_ETH_MCLK			0
82 #define CLK_ETH_PLL1			1
83 #define CLK_ETH_PLL2			2
84 
85 #define MDIV_SHIFT_ETH			3
86 #define DIV_SHIFT_ETH			6
87 #define DIV_ETH_125			9
88 #define DIV_ETH_50			12
89 #define DIV_ETH_P2P			15
90 
91 #define ETH_CLK_CFG			(4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \
92 					| 1 << DIV_ETH_125 \
93 					| 0 << DIV_SHIFT_ETH \
94 					| 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1)
95  /* CGU Ethernet control */
96 
97 #define ETH_CLK_TX_EXT_PHY		0
98 #define ETH_CLK_TX_125M			1
99 #define ETH_CLK_TX_25M			2
100 #define ETH_CLK_TX_2M5			3
101 #define ETH_CLK_TX_DIS			7
102 
103 #define ETH_CLK_RX_EXT_PHY		0
104 #define ETH_CLK_RX_25M			1
105 #define ETH_CLK_RX_2M5			2
106 #define ETH_CLK_RX_DIS			3
107 #define RX_CLK_SHIFT			3
108 #define ETH_CLK_MASK			~(0x1F)
109 
110 #define ETH_PHY_MODE_GMII		0
111 #define ETH_PHY_MODE_RMII		1
112 #define ETH_PHY_CLK_DIS			1
113 
114 #define ETH_CLK_CTRL			(ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \
115 					| ETH_CLK_TX_EXT_PHY)
116 /* CGU qspi clock */
117 #define DIV_HCLK1_SHIFT			9
118 #define DIV_CRYP_SHIFT			6
119 #define MDIV_QSPI_SHIFT			3
120 
121 #define CLK_QSPI_OSC			0
122 #define CLK_QSPI_MCLK			1
123 #define CLK_QSPI_PLL1			2
124 #define CLK_QSPI_PLL2			3
125 
126 #define QSPI_CLK_CTRL			(3 << DIV_HCLK1_SHIFT \
127 					| 1 << DIV_CRYP_SHIFT \
128 					| 0 << MDIV_QSPI_SHIFT \
129 					| CLK_QSPI_OSC)
130 
131 #endif
132