1 /*
2  * (C) Copyright 2016
3  * Michael Kurz, michi.kurz@gmail.com.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _STM32_SYSCFG_H
9 #define _STM32_SYSCFG_H
10 
11 struct stm32_syscfg_regs {
12 	u32 memrmp;
13 	u32 pmc;
14 	u32 exticr1;
15 	u32 exticr2;
16 	u32 exticr3;
17 	u32 exticr4;
18 	u32 cmpcr;
19 };
20 
21 /*
22  * SYSCFG registers base
23  */
24 #define STM32_SYSCFG		((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE)
25 
26 /* SYSCFG memory remap register */
27 #define SYSCFG_MEMRMP_MEM_BOOT	BIT(0)
28 #define SYSCFG_MEMRMP_SWP_FMC	BIT(10)
29 
30 /* SYSCFG peripheral mode configuration register */
31 #define SYSCFG_PMC_ADCXDC2	BIT(16)
32 #define SYSCFG_PMC_MII_RMII_SEL	BIT(23)
33 
34 /* Compensation cell control register */
35 #define SYSCFG_CMPCR_CMP_PD	BIT(0)
36 #define SYSCFG_CMPCR_READY	BIT(8)
37 
38 #endif
39