1*d0a768b1SPatrice Chotard /* 2*d0a768b1SPatrice Chotard * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 3*d0a768b1SPatrice Chotard * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. 4*d0a768b1SPatrice Chotard * 5*d0a768b1SPatrice Chotard * SPDX-License-Identifier: GPL-2.0+ 6*d0a768b1SPatrice Chotard */ 7*d0a768b1SPatrice Chotard 8*d0a768b1SPatrice Chotard #ifndef __STM32_PWR_H_ 9*d0a768b1SPatrice Chotard 10*d0a768b1SPatrice Chotard /* 11*d0a768b1SPatrice Chotard * Offsets of some PWR registers 12*d0a768b1SPatrice Chotard */ 13*d0a768b1SPatrice Chotard #define PWR_CR1_ODEN BIT(16) 14*d0a768b1SPatrice Chotard #define PWR_CR1_ODSWEN BIT(17) 15*d0a768b1SPatrice Chotard #define PWR_CSR1_ODRDY BIT(16) 16*d0a768b1SPatrice Chotard #define PWR_CSR1_ODSWRDY BIT(17) 17*d0a768b1SPatrice Chotard 18*d0a768b1SPatrice Chotard struct stm32_pwr_regs { 19*d0a768b1SPatrice Chotard u32 cr1; /* power control register 1 */ 20*d0a768b1SPatrice Chotard u32 csr1; /* power control/status register 2 */ 21*d0a768b1SPatrice Chotard u32 cr2; /* power control register 2 */ 22*d0a768b1SPatrice Chotard u32 csr2; /* power control/status register 2 */ 23*d0a768b1SPatrice Chotard }; 24*d0a768b1SPatrice Chotard 25*d0a768b1SPatrice Chotard #endif /* __STM32_PWR_H_ */ 26