1 /* 2 * (C) Copyright 2016 3 * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _ASM_ARCH_HARDWARE_H 9 #define _ASM_ARCH_HARDWARE_H 10 11 /* STM32F746 */ 12 #define ITCM_FLASH_BASE 0x00200000UL 13 #define AXIM_FLASH_BASE 0x08000000UL 14 15 #define ITCM_SRAM_BASE 0x00000000UL 16 #define DTCM_SRAM_BASE 0x20000000UL 17 #define SRAM1_BASE 0x20010000UL 18 #define SRAM2_BASE 0x2004C000UL 19 20 #define PERIPH_BASE 0x40000000UL 21 22 #define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) 23 #define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000) 24 #define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000) 25 #define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000) 26 #define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000) 27 28 #define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) 29 #define USART2_BASE (APB1_PERIPH_BASE + 0x4400) 30 #define USART3_BASE (APB1_PERIPH_BASE + 0x4800) 31 #define PWR_BASE (APB1_PERIPH_BASE + 0x7000) 32 33 #define USART1_BASE (APB2_PERIPH_BASE + 0x1000) 34 #define USART6_BASE (APB2_PERIPH_BASE + 0x1400) 35 #define STM32_SYSCFG_BASE (APB2_PERIPH_BASE + 0x3800) 36 37 #define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000) 38 #define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400) 39 #define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800) 40 #define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00) 41 #define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000) 42 #define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400) 43 #define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800) 44 #define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00) 45 #define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000) 46 #define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400) 47 #define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800) 48 #define RCC_BASE (AHB1_PERIPH_BASE + 0x3800) 49 #define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00) 50 51 52 #define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x40000140) 53 54 static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { 55 [0 ... 3] = 32 * 1024, 56 [4] = 128 * 1024, 57 [5 ... 7] = 256 * 1024 58 }; 59 60 enum clock { 61 CLOCK_CORE, 62 CLOCK_AHB, 63 CLOCK_APB1, 64 CLOCK_APB2 65 }; 66 #define STM32_BUS_MASK GENMASK(31, 16) 67 68 struct stm32_rcc_regs { 69 u32 cr; /* RCC clock control */ 70 u32 pllcfgr; /* RCC PLL configuration */ 71 u32 cfgr; /* RCC clock configuration */ 72 u32 cir; /* RCC clock interrupt */ 73 u32 ahb1rstr; /* RCC AHB1 peripheral reset */ 74 u32 ahb2rstr; /* RCC AHB2 peripheral reset */ 75 u32 ahb3rstr; /* RCC AHB3 peripheral reset */ 76 u32 rsv0; 77 u32 apb1rstr; /* RCC APB1 peripheral reset */ 78 u32 apb2rstr; /* RCC APB2 peripheral reset */ 79 u32 rsv1[2]; 80 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ 81 u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ 82 u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ 83 u32 rsv2; 84 u32 apb1enr; /* RCC APB1 peripheral clock enable */ 85 u32 apb2enr; /* RCC APB2 peripheral clock enable */ 86 u32 rsv3[2]; 87 u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ 88 u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ 89 u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ 90 u32 rsv4; 91 u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ 92 u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ 93 u32 rsv5[2]; 94 u32 bdcr; /* RCC Backup domain control */ 95 u32 csr; /* RCC clock control & status */ 96 u32 rsv6[2]; 97 u32 sscgr; /* RCC spread spectrum clock generation */ 98 u32 plli2scfgr; /* RCC PLLI2S configuration */ 99 u32 pllsaicfgr; /* PLLSAI configuration */ 100 u32 dckcfgr; /* dedicated clocks configuration register */ 101 }; 102 #define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE) 103 104 struct stm32_rcc_ext_f7_regs { 105 u32 dckcfgr2; /* dedicated clocks configuration register */ 106 }; 107 #define STM32_RCC_EXT_F7 ((struct stm32_rcc_ext_f7_regs *) (RCC_BASE + sizeof(struct stm32_rcc_regs))) 108 109 struct stm32_pwr_regs { 110 u32 cr1; /* power control register 1 */ 111 u32 csr1; /* power control/status register 2 */ 112 u32 cr2; /* power control register 2 */ 113 u32 csr2; /* power control/status register 2 */ 114 }; 115 #define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE) 116 117 int configure_clocks(void); 118 unsigned long clock_get(enum clock clck); 119 void stm32_flash_latency_cfg(int latency); 120 121 #endif /* _ASM_ARCH_HARDWARE_H */ 122