1 /*
2  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
3  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
4  *
5  * SPDX-License-Identifier:	GPL-2.0+
6  */
7 
8 #ifndef _ASM_ARCH_HARDWARE_H
9 #define _ASM_ARCH_HARDWARE_H
10 
11 /* STM32F746 */
12 #define ITCM_FLASH_BASE		0x00200000UL
13 #define AXIM_FLASH_BASE		0x08000000UL
14 
15 #define ITCM_SRAM_BASE		0x00000000UL
16 #define DTCM_SRAM_BASE		0x20000000UL
17 #define SRAM1_BASE		0x20010000UL
18 #define SRAM2_BASE		0x2004C000UL
19 
20 #define PERIPH_BASE		0x40000000UL
21 
22 #define APB1_PERIPH_BASE	(PERIPH_BASE + 0x00000000)
23 #define APB2_PERIPH_BASE	(PERIPH_BASE + 0x00010000)
24 #define AHB1_PERIPH_BASE	(PERIPH_BASE + 0x00020000)
25 #define AHB2_PERIPH_BASE	(PERIPH_BASE + 0x10000000)
26 #define AHB3_PERIPH_BASE	(PERIPH_BASE + 0x20000000)
27 
28 #define USART2_BASE		(APB1_PERIPH_BASE + 0x4400)
29 #define USART3_BASE		(APB1_PERIPH_BASE + 0x4800)
30 #define PWR_BASE		(APB1_PERIPH_BASE + 0x7000)
31 
32 #define USART1_BASE		(APB2_PERIPH_BASE + 0x1000)
33 #define USART6_BASE		(APB2_PERIPH_BASE + 0x1400)
34 #define STM32_SYSCFG_BASE	(APB2_PERIPH_BASE + 0x3800)
35 
36 #define STM32_GPIOA_BASE	(AHB1_PERIPH_BASE + 0x0000)
37 #define STM32_GPIOB_BASE	(AHB1_PERIPH_BASE + 0x0400)
38 #define STM32_GPIOC_BASE	(AHB1_PERIPH_BASE + 0x0800)
39 #define STM32_GPIOD_BASE	(AHB1_PERIPH_BASE + 0x0C00)
40 #define STM32_GPIOE_BASE	(AHB1_PERIPH_BASE + 0x1000)
41 #define STM32_GPIOF_BASE	(AHB1_PERIPH_BASE + 0x1400)
42 #define STM32_GPIOG_BASE	(AHB1_PERIPH_BASE + 0x1800)
43 #define STM32_GPIOH_BASE	(AHB1_PERIPH_BASE + 0x1C00)
44 #define STM32_GPIOI_BASE	(AHB1_PERIPH_BASE + 0x2000)
45 #define STM32_GPIOJ_BASE	(AHB1_PERIPH_BASE + 0x2400)
46 #define STM32_GPIOK_BASE	(AHB1_PERIPH_BASE + 0x2800)
47 #define FLASH_CNTL_BASE		(AHB1_PERIPH_BASE + 0x3C00)
48 
49 
50 #define SDRAM_FMC_BASE		(AHB3_PERIPH_BASE + 0x40000140)
51 
52 static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
53 	[0 ... 3] =	32 * 1024,
54 	[4] =		128 * 1024,
55 	[5 ... 7] =	256 * 1024
56 };
57 
58 #define STM32_BUS_MASK		GENMASK(31, 16)
59 
60 void stm32_flash_latency_cfg(int latency);
61 
62 #endif /* _ASM_ARCH_HARDWARE_H */
63