1 /*
2  * (C) Copyright 2011
3  * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
4  *
5  * (C) Copyright 2015
6  * Kamil Lulko, <rev13@wp.pl>
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef _MACH_STM32_H_
12 #define _MACH_STM32_H_
13 
14 /*
15  * Peripheral memory map
16  */
17 #define STM32_PERIPH_BASE	0x40000000
18 #define STM32_APB1PERIPH_BASE	(STM32_PERIPH_BASE + 0x00000000)
19 #define STM32_APB2PERIPH_BASE	(STM32_PERIPH_BASE + 0x00010000)
20 #define STM32_AHB1PERIPH_BASE	(STM32_PERIPH_BASE + 0x00020000)
21 #define STM32_AHB2PERIPH_BASE	(STM32_PERIPH_BASE + 0x10000000)
22 
23 #define STM32_BUS_MASK		0xFFFF0000
24 
25 /*
26  * Register maps
27  */
28 struct stm32_rcc_regs {
29 	u32 cr;		/* RCC clock control */
30 	u32 pllcfgr;	/* RCC PLL configuration */
31 	u32 cfgr;	/* RCC clock configuration */
32 	u32 cir;	/* RCC clock interrupt */
33 	u32 ahb1rstr;	/* RCC AHB1 peripheral reset */
34 	u32 ahb2rstr;	/* RCC AHB2 peripheral reset */
35 	u32 ahb3rstr;	/* RCC AHB3 peripheral reset */
36 	u32 rsv0;
37 	u32 apb1rstr;	/* RCC APB1 peripheral reset */
38 	u32 apb2rstr;	/* RCC APB2 peripheral reset */
39 	u32 rsv1[2];
40 	u32 ahb1enr;	/* RCC AHB1 peripheral clock enable */
41 	u32 ahb2enr;	/* RCC AHB2 peripheral clock enable */
42 	u32 ahb3enr;	/* RCC AHB3 peripheral clock enable */
43 	u32 rsv2;
44 	u32 apb1enr;	/* RCC APB1 peripheral clock enable */
45 	u32 apb2enr;	/* RCC APB2 peripheral clock enable */
46 	u32 rsv3[2];
47 	u32 ahb1lpenr;	/* RCC AHB1 periph clk enable in low pwr mode */
48 	u32 ahb2lpenr;	/* RCC AHB2 periph clk enable in low pwr mode */
49 	u32 ahb3lpenr;	/* RCC AHB3 periph clk enable in low pwr mode */
50 	u32 rsv4;
51 	u32 apb1lpenr;	/* RCC APB1 periph clk enable in low pwr mode */
52 	u32 apb2lpenr;	/* RCC APB2 periph clk enable in low pwr mode */
53 	u32 rsv5[2];
54 	u32 bdcr;	/* RCC Backup domain control */
55 	u32 csr;	/* RCC clock control & status */
56 	u32 rsv6[2];
57 	u32 sscgr;	/* RCC spread spectrum clock generation */
58 	u32 plli2scfgr;	/* RCC PLLI2S configuration */
59 	u32 pllsaicfgr;
60 	u32 dckcfgr;
61 };
62 
63 struct stm32_pwr_regs {
64 	u32 cr;
65 	u32 csr;
66 };
67 
68 struct stm32_flash_regs {
69 	u32 acr;
70 	u32 key;
71 	u32 optkeyr;
72 	u32 sr;
73 	u32 cr;
74 	u32 optcr;
75 	u32 optcr1;
76 };
77 
78 /*
79  * Registers access macros
80  */
81 #define STM32_RCC_BASE		(STM32_AHB1PERIPH_BASE + 0x3800)
82 #define STM32_RCC		((struct stm32_rcc_regs *)STM32_RCC_BASE)
83 
84 #define STM32_PWR_BASE		(STM32_APB1PERIPH_BASE + 0x7000)
85 #define STM32_PWR		((struct stm32_pwr_regs *)STM32_PWR_BASE)
86 
87 #define STM32_FLASH_BASE	(STM32_AHB1PERIPH_BASE + 0x3C00)
88 #define STM32_FLASH		((struct stm32_flash_regs *)STM32_FLASH_BASE)
89 
90 #define STM32_FLASH_SR_BSY		(1 << 16)
91 
92 #define STM32_FLASH_CR_PG		(1 << 0)
93 #define STM32_FLASH_CR_SER		(1 << 1)
94 #define STM32_FLASH_CR_STRT		(1 << 16)
95 #define STM32_FLASH_CR_LOCK		(1 << 31)
96 #define STM32_FLASH_CR_SNB_OFFSET	3
97 
98 enum clock {
99 	CLOCK_CORE,
100 	CLOCK_AHB,
101 	CLOCK_APB1,
102 	CLOCK_APB2
103 };
104 
105 int configure_clocks(void);
106 unsigned long clock_get(enum clock clck);
107 
108 #endif /* _MACH_STM32_H_ */
109