1 /*
2  * (C) Copyright 2011
3  * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
4  *
5  * (C) Copyright 2015
6  * Kamil Lulko, <kamil.lulko@gmail.com>
7  *
8  * SPDX-License-Identifier:	GPL-2.0+
9  */
10 
11 #ifndef _MACH_STM32_H_
12 #define _MACH_STM32_H_
13 
14 /*
15  * Peripheral memory map
16  */
17 #define STM32_SYSMEM_BASE	0x1FFF0000
18 #define STM32_PERIPH_BASE	0x40000000
19 #define STM32_APB1PERIPH_BASE	(STM32_PERIPH_BASE + 0x00000000)
20 #define STM32_APB2PERIPH_BASE	(STM32_PERIPH_BASE + 0x00010000)
21 #define STM32_AHB1PERIPH_BASE	(STM32_PERIPH_BASE + 0x00020000)
22 #define STM32_AHB2PERIPH_BASE	(STM32_PERIPH_BASE + 0x10000000)
23 
24 #define STM32_BUS_MASK		0xFFFF0000
25 
26 /*
27  * Register maps
28  */
29 struct stm32_u_id_regs {
30 	u32 u_id_low;
31 	u32 u_id_mid;
32 	u32 u_id_high;
33 };
34 
35 /*
36  * Registers access macros
37  */
38 #define STM32_U_ID_BASE		(STM32_SYSMEM_BASE + 0x7A10)
39 #define STM32_U_ID		((struct stm32_u_id_regs *)STM32_U_ID_BASE)
40 
41 #define STM32_RCC_BASE		(STM32_AHB1PERIPH_BASE + 0x3800)
42 #define STM32_RCC		((struct stm32_rcc_regs *)STM32_RCC_BASE)
43 
44 #define FLASH_CNTL_BASE		(STM32_AHB1PERIPH_BASE + 0x3C00)
45 
46 static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
47 	[0 ... 3] =	16 * 1024,
48 	[4] =		64 * 1024,
49 	[5 ... 11] =	128 * 1024
50 };
51 
52 void stm32_flash_latency_cfg(int latency);
53 
54 #endif /* _MACH_STM32_H_ */
55