1 /* 2 * (C) Copyright 2011 3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4 * 5 * (C) Copyright 2015 6 * Kamil Lulko, <kamil.lulko@gmail.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _MACH_STM32_H_ 12 #define _MACH_STM32_H_ 13 14 /* 15 * Peripheral memory map 16 */ 17 #define STM32_SYSMEM_BASE 0x1FFF0000 18 #define STM32_PERIPH_BASE 0x40000000 19 #define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) 20 #define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) 21 #define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000) 22 #define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000) 23 24 #define STM32_BUS_MASK 0xFFFF0000 25 26 #define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000) 27 #define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400) 28 #define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800) 29 #define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00) 30 #define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000) 31 #define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400) 32 #define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800) 33 #define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00) 34 #define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000) 35 36 /* 37 * Register maps 38 */ 39 struct stm32_u_id_regs { 40 u32 u_id_low; 41 u32 u_id_mid; 42 u32 u_id_high; 43 }; 44 45 /* 46 * Registers access macros 47 */ 48 #define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10) 49 #define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE) 50 51 #define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800) 52 #define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE) 53 54 #define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00) 55 56 static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { 57 [0 ... 3] = 16 * 1024, 58 [4] = 64 * 1024, 59 [5 ... 11] = 128 * 1024 60 }; 61 62 void stm32_flash_latency_cfg(int latency); 63 64 #endif /* _MACH_STM32_H_ */ 65