1 /* 2 * (C) Copyright 2011 3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4 * 5 * (C) Copyright 2015 6 * Kamil Lulko, <kamil.lulko@gmail.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef _MACH_STM32_H_ 12 #define _MACH_STM32_H_ 13 14 /* 15 * Peripheral memory map 16 */ 17 #define STM32_SYSMEM_BASE 0x1FFF0000 18 #define STM32_PERIPH_BASE 0x40000000 19 #define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) 20 #define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) 21 #define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000) 22 #define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000) 23 24 #define STM32_BUS_MASK 0xFFFF0000 25 26 #define STM32_GPIOA_BASE (STM32_AHB1PERIPH_BASE + 0x0000) 27 #define STM32_GPIOB_BASE (STM32_AHB1PERIPH_BASE + 0x0400) 28 #define STM32_GPIOC_BASE (STM32_AHB1PERIPH_BASE + 0x0800) 29 #define STM32_GPIOD_BASE (STM32_AHB1PERIPH_BASE + 0x0C00) 30 #define STM32_GPIOE_BASE (STM32_AHB1PERIPH_BASE + 0x1000) 31 #define STM32_GPIOF_BASE (STM32_AHB1PERIPH_BASE + 0x1400) 32 #define STM32_GPIOG_BASE (STM32_AHB1PERIPH_BASE + 0x1800) 33 #define STM32_GPIOH_BASE (STM32_AHB1PERIPH_BASE + 0x1C00) 34 #define STM32_GPIOI_BASE (STM32_AHB1PERIPH_BASE + 0x2000) 35 36 /* 37 * Register maps 38 */ 39 struct stm32_u_id_regs { 40 u32 u_id_low; 41 u32 u_id_mid; 42 u32 u_id_high; 43 }; 44 45 struct stm32_rcc_regs { 46 u32 cr; /* RCC clock control */ 47 u32 pllcfgr; /* RCC PLL configuration */ 48 u32 cfgr; /* RCC clock configuration */ 49 u32 cir; /* RCC clock interrupt */ 50 u32 ahb1rstr; /* RCC AHB1 peripheral reset */ 51 u32 ahb2rstr; /* RCC AHB2 peripheral reset */ 52 u32 ahb3rstr; /* RCC AHB3 peripheral reset */ 53 u32 rsv0; 54 u32 apb1rstr; /* RCC APB1 peripheral reset */ 55 u32 apb2rstr; /* RCC APB2 peripheral reset */ 56 u32 rsv1[2]; 57 u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ 58 u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ 59 u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ 60 u32 rsv2; 61 u32 apb1enr; /* RCC APB1 peripheral clock enable */ 62 u32 apb2enr; /* RCC APB2 peripheral clock enable */ 63 u32 rsv3[2]; 64 u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ 65 u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ 66 u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ 67 u32 rsv4; 68 u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ 69 u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ 70 u32 rsv5[2]; 71 u32 bdcr; /* RCC Backup domain control */ 72 u32 csr; /* RCC clock control & status */ 73 u32 rsv6[2]; 74 u32 sscgr; /* RCC spread spectrum clock generation */ 75 u32 plli2scfgr; /* RCC PLLI2S configuration */ 76 u32 pllsaicfgr; 77 u32 dckcfgr; 78 }; 79 80 struct stm32_pwr_regs { 81 u32 cr; 82 u32 csr; 83 }; 84 85 /* 86 * Registers access macros 87 */ 88 #define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10) 89 #define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE) 90 91 #define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800) 92 #define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE) 93 94 #define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000) 95 #define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE) 96 97 /* 98 * Peripheral base addresses 99 */ 100 #define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000) 101 #define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400) 102 #define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800) 103 #define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400) 104 105 #define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00) 106 107 static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = { 108 [0 ... 3] = 16 * 1024, 109 [4] = 64 * 1024, 110 [5 ... 11] = 128 * 1024 111 }; 112 113 enum clock { 114 CLOCK_CORE, 115 CLOCK_AHB, 116 CLOCK_APB1, 117 CLOCK_APB2 118 }; 119 120 int configure_clocks(void); 121 unsigned long clock_get(enum clock clck); 122 void stm32_flash_latency_cfg(int latency); 123 124 #endif /* _MACH_STM32_H_ */ 125