1eaaa4f7eSrev13@wp.pl /* 2eaaa4f7eSrev13@wp.pl * (C) Copyright 2011 3eaaa4f7eSrev13@wp.pl * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4eaaa4f7eSrev13@wp.pl * 5eaaa4f7eSrev13@wp.pl * (C) Copyright 2015 6eaaa4f7eSrev13@wp.pl * Kamil Lulko, <rev13@wp.pl> 7eaaa4f7eSrev13@wp.pl * 8eaaa4f7eSrev13@wp.pl * SPDX-License-Identifier: GPL-2.0+ 9eaaa4f7eSrev13@wp.pl */ 10eaaa4f7eSrev13@wp.pl 11eaaa4f7eSrev13@wp.pl #ifndef _MACH_STM32_H_ 12eaaa4f7eSrev13@wp.pl #define _MACH_STM32_H_ 13eaaa4f7eSrev13@wp.pl 14eaaa4f7eSrev13@wp.pl /* 15eaaa4f7eSrev13@wp.pl * Peripheral memory map 16eaaa4f7eSrev13@wp.pl */ 17089fddfdSAntonio Borneo #define STM32_SYSMEM_BASE 0x1FFF0000 18eaaa4f7eSrev13@wp.pl #define STM32_PERIPH_BASE 0x40000000 19eaaa4f7eSrev13@wp.pl #define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) 20eaaa4f7eSrev13@wp.pl #define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) 21eaaa4f7eSrev13@wp.pl #define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000) 22eaaa4f7eSrev13@wp.pl #define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000) 23eaaa4f7eSrev13@wp.pl 24eaaa4f7eSrev13@wp.pl #define STM32_BUS_MASK 0xFFFF0000 25eaaa4f7eSrev13@wp.pl 26eaaa4f7eSrev13@wp.pl /* 27eaaa4f7eSrev13@wp.pl * Register maps 28eaaa4f7eSrev13@wp.pl */ 29089fddfdSAntonio Borneo struct stm32_u_id_regs { 30089fddfdSAntonio Borneo u32 u_id_low; 31089fddfdSAntonio Borneo u32 u_id_mid; 32089fddfdSAntonio Borneo u32 u_id_high; 33089fddfdSAntonio Borneo }; 34089fddfdSAntonio Borneo 35eaaa4f7eSrev13@wp.pl struct stm32_rcc_regs { 36eaaa4f7eSrev13@wp.pl u32 cr; /* RCC clock control */ 37eaaa4f7eSrev13@wp.pl u32 pllcfgr; /* RCC PLL configuration */ 38eaaa4f7eSrev13@wp.pl u32 cfgr; /* RCC clock configuration */ 39eaaa4f7eSrev13@wp.pl u32 cir; /* RCC clock interrupt */ 40eaaa4f7eSrev13@wp.pl u32 ahb1rstr; /* RCC AHB1 peripheral reset */ 41eaaa4f7eSrev13@wp.pl u32 ahb2rstr; /* RCC AHB2 peripheral reset */ 42eaaa4f7eSrev13@wp.pl u32 ahb3rstr; /* RCC AHB3 peripheral reset */ 43eaaa4f7eSrev13@wp.pl u32 rsv0; 44eaaa4f7eSrev13@wp.pl u32 apb1rstr; /* RCC APB1 peripheral reset */ 45eaaa4f7eSrev13@wp.pl u32 apb2rstr; /* RCC APB2 peripheral reset */ 46eaaa4f7eSrev13@wp.pl u32 rsv1[2]; 47eaaa4f7eSrev13@wp.pl u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ 48eaaa4f7eSrev13@wp.pl u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ 49eaaa4f7eSrev13@wp.pl u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ 50eaaa4f7eSrev13@wp.pl u32 rsv2; 51eaaa4f7eSrev13@wp.pl u32 apb1enr; /* RCC APB1 peripheral clock enable */ 52eaaa4f7eSrev13@wp.pl u32 apb2enr; /* RCC APB2 peripheral clock enable */ 53eaaa4f7eSrev13@wp.pl u32 rsv3[2]; 54eaaa4f7eSrev13@wp.pl u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ 55eaaa4f7eSrev13@wp.pl u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ 56eaaa4f7eSrev13@wp.pl u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ 57eaaa4f7eSrev13@wp.pl u32 rsv4; 58eaaa4f7eSrev13@wp.pl u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ 59eaaa4f7eSrev13@wp.pl u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ 60eaaa4f7eSrev13@wp.pl u32 rsv5[2]; 61eaaa4f7eSrev13@wp.pl u32 bdcr; /* RCC Backup domain control */ 62eaaa4f7eSrev13@wp.pl u32 csr; /* RCC clock control & status */ 63eaaa4f7eSrev13@wp.pl u32 rsv6[2]; 64eaaa4f7eSrev13@wp.pl u32 sscgr; /* RCC spread spectrum clock generation */ 65eaaa4f7eSrev13@wp.pl u32 plli2scfgr; /* RCC PLLI2S configuration */ 66eaaa4f7eSrev13@wp.pl u32 pllsaicfgr; 67eaaa4f7eSrev13@wp.pl u32 dckcfgr; 68eaaa4f7eSrev13@wp.pl }; 69eaaa4f7eSrev13@wp.pl 70eaaa4f7eSrev13@wp.pl struct stm32_pwr_regs { 71eaaa4f7eSrev13@wp.pl u32 cr; 72eaaa4f7eSrev13@wp.pl u32 csr; 73eaaa4f7eSrev13@wp.pl }; 74eaaa4f7eSrev13@wp.pl 75eaaa4f7eSrev13@wp.pl struct stm32_flash_regs { 76eaaa4f7eSrev13@wp.pl u32 acr; 77eaaa4f7eSrev13@wp.pl u32 key; 78eaaa4f7eSrev13@wp.pl u32 optkeyr; 79eaaa4f7eSrev13@wp.pl u32 sr; 80eaaa4f7eSrev13@wp.pl u32 cr; 81eaaa4f7eSrev13@wp.pl u32 optcr; 82eaaa4f7eSrev13@wp.pl u32 optcr1; 83eaaa4f7eSrev13@wp.pl }; 84eaaa4f7eSrev13@wp.pl 85eaaa4f7eSrev13@wp.pl /* 86eaaa4f7eSrev13@wp.pl * Registers access macros 87eaaa4f7eSrev13@wp.pl */ 88089fddfdSAntonio Borneo #define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10) 89089fddfdSAntonio Borneo #define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE) 90089fddfdSAntonio Borneo 91eaaa4f7eSrev13@wp.pl #define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800) 92eaaa4f7eSrev13@wp.pl #define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE) 93eaaa4f7eSrev13@wp.pl 94eaaa4f7eSrev13@wp.pl #define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000) 95eaaa4f7eSrev13@wp.pl #define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE) 96eaaa4f7eSrev13@wp.pl 97eaaa4f7eSrev13@wp.pl #define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0x3C00) 98eaaa4f7eSrev13@wp.pl #define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE) 99eaaa4f7eSrev13@wp.pl 100eaaa4f7eSrev13@wp.pl #define STM32_FLASH_SR_BSY (1 << 16) 101eaaa4f7eSrev13@wp.pl 102eaaa4f7eSrev13@wp.pl #define STM32_FLASH_CR_PG (1 << 0) 103eaaa4f7eSrev13@wp.pl #define STM32_FLASH_CR_SER (1 << 1) 104eaaa4f7eSrev13@wp.pl #define STM32_FLASH_CR_STRT (1 << 16) 105eaaa4f7eSrev13@wp.pl #define STM32_FLASH_CR_LOCK (1 << 31) 106eaaa4f7eSrev13@wp.pl #define STM32_FLASH_CR_SNB_OFFSET 3 107*43fb0e39SVadzim Dambrouski #define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET) 108eaaa4f7eSrev13@wp.pl 109eaaa4f7eSrev13@wp.pl enum clock { 110eaaa4f7eSrev13@wp.pl CLOCK_CORE, 111eaaa4f7eSrev13@wp.pl CLOCK_AHB, 112eaaa4f7eSrev13@wp.pl CLOCK_APB1, 113eaaa4f7eSrev13@wp.pl CLOCK_APB2 114eaaa4f7eSrev13@wp.pl }; 115eaaa4f7eSrev13@wp.pl 116eaaa4f7eSrev13@wp.pl int configure_clocks(void); 117eaaa4f7eSrev13@wp.pl unsigned long clock_get(enum clock clck); 118eaaa4f7eSrev13@wp.pl 119eaaa4f7eSrev13@wp.pl #endif /* _MACH_STM32_H_ */ 120