1*eaaa4f7eSrev13@wp.pl /* 2*eaaa4f7eSrev13@wp.pl * (C) Copyright 2011 3*eaaa4f7eSrev13@wp.pl * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com 4*eaaa4f7eSrev13@wp.pl * 5*eaaa4f7eSrev13@wp.pl * (C) Copyright 2015 6*eaaa4f7eSrev13@wp.pl * Kamil Lulko, <rev13@wp.pl> 7*eaaa4f7eSrev13@wp.pl * 8*eaaa4f7eSrev13@wp.pl * SPDX-License-Identifier: GPL-2.0+ 9*eaaa4f7eSrev13@wp.pl */ 10*eaaa4f7eSrev13@wp.pl 11*eaaa4f7eSrev13@wp.pl #ifndef _STM32_GPIO_H_ 12*eaaa4f7eSrev13@wp.pl #define _STM32_GPIO_H_ 13*eaaa4f7eSrev13@wp.pl 14*eaaa4f7eSrev13@wp.pl enum stm32_gpio_port { 15*eaaa4f7eSrev13@wp.pl STM32_GPIO_PORT_A = 0, 16*eaaa4f7eSrev13@wp.pl STM32_GPIO_PORT_B, 17*eaaa4f7eSrev13@wp.pl STM32_GPIO_PORT_C, 18*eaaa4f7eSrev13@wp.pl STM32_GPIO_PORT_D, 19*eaaa4f7eSrev13@wp.pl STM32_GPIO_PORT_E, 20*eaaa4f7eSrev13@wp.pl STM32_GPIO_PORT_F, 21*eaaa4f7eSrev13@wp.pl STM32_GPIO_PORT_G, 22*eaaa4f7eSrev13@wp.pl STM32_GPIO_PORT_H, 23*eaaa4f7eSrev13@wp.pl STM32_GPIO_PORT_I 24*eaaa4f7eSrev13@wp.pl }; 25*eaaa4f7eSrev13@wp.pl 26*eaaa4f7eSrev13@wp.pl enum stm32_gpio_pin { 27*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_0 = 0, 28*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_1, 29*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_2, 30*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_3, 31*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_4, 32*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_5, 33*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_6, 34*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_7, 35*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_8, 36*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_9, 37*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_10, 38*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_11, 39*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_12, 40*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_13, 41*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_14, 42*eaaa4f7eSrev13@wp.pl STM32_GPIO_PIN_15 43*eaaa4f7eSrev13@wp.pl }; 44*eaaa4f7eSrev13@wp.pl 45*eaaa4f7eSrev13@wp.pl enum stm32_gpio_mode { 46*eaaa4f7eSrev13@wp.pl STM32_GPIO_MODE_IN = 0, 47*eaaa4f7eSrev13@wp.pl STM32_GPIO_MODE_OUT, 48*eaaa4f7eSrev13@wp.pl STM32_GPIO_MODE_AF, 49*eaaa4f7eSrev13@wp.pl STM32_GPIO_MODE_AN 50*eaaa4f7eSrev13@wp.pl }; 51*eaaa4f7eSrev13@wp.pl 52*eaaa4f7eSrev13@wp.pl enum stm32_gpio_otype { 53*eaaa4f7eSrev13@wp.pl STM32_GPIO_OTYPE_PP = 0, 54*eaaa4f7eSrev13@wp.pl STM32_GPIO_OTYPE_OD 55*eaaa4f7eSrev13@wp.pl }; 56*eaaa4f7eSrev13@wp.pl 57*eaaa4f7eSrev13@wp.pl enum stm32_gpio_speed { 58*eaaa4f7eSrev13@wp.pl STM32_GPIO_SPEED_2M = 0, 59*eaaa4f7eSrev13@wp.pl STM32_GPIO_SPEED_25M, 60*eaaa4f7eSrev13@wp.pl STM32_GPIO_SPEED_50M, 61*eaaa4f7eSrev13@wp.pl STM32_GPIO_SPEED_100M 62*eaaa4f7eSrev13@wp.pl }; 63*eaaa4f7eSrev13@wp.pl 64*eaaa4f7eSrev13@wp.pl enum stm32_gpio_pupd { 65*eaaa4f7eSrev13@wp.pl STM32_GPIO_PUPD_NO = 0, 66*eaaa4f7eSrev13@wp.pl STM32_GPIO_PUPD_UP, 67*eaaa4f7eSrev13@wp.pl STM32_GPIO_PUPD_DOWN 68*eaaa4f7eSrev13@wp.pl }; 69*eaaa4f7eSrev13@wp.pl 70*eaaa4f7eSrev13@wp.pl enum stm32_gpio_af { 71*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF0 = 0, 72*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF1, 73*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF2, 74*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF3, 75*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF4, 76*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF5, 77*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF6, 78*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF7, 79*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF8, 80*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF9, 81*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF10, 82*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF11, 83*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF12, 84*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF13, 85*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF14, 86*eaaa4f7eSrev13@wp.pl STM32_GPIO_AF15 87*eaaa4f7eSrev13@wp.pl }; 88*eaaa4f7eSrev13@wp.pl 89*eaaa4f7eSrev13@wp.pl struct stm32_gpio_dsc { 90*eaaa4f7eSrev13@wp.pl enum stm32_gpio_port port; 91*eaaa4f7eSrev13@wp.pl enum stm32_gpio_pin pin; 92*eaaa4f7eSrev13@wp.pl }; 93*eaaa4f7eSrev13@wp.pl 94*eaaa4f7eSrev13@wp.pl struct stm32_gpio_ctl { 95*eaaa4f7eSrev13@wp.pl enum stm32_gpio_mode mode; 96*eaaa4f7eSrev13@wp.pl enum stm32_gpio_otype otype; 97*eaaa4f7eSrev13@wp.pl enum stm32_gpio_speed speed; 98*eaaa4f7eSrev13@wp.pl enum stm32_gpio_pupd pupd; 99*eaaa4f7eSrev13@wp.pl enum stm32_gpio_af af; 100*eaaa4f7eSrev13@wp.pl }; 101*eaaa4f7eSrev13@wp.pl 102*eaaa4f7eSrev13@wp.pl static inline unsigned stm32_gpio_to_port(unsigned gpio) 103*eaaa4f7eSrev13@wp.pl { 104*eaaa4f7eSrev13@wp.pl return gpio / 16; 105*eaaa4f7eSrev13@wp.pl } 106*eaaa4f7eSrev13@wp.pl 107*eaaa4f7eSrev13@wp.pl static inline unsigned stm32_gpio_to_pin(unsigned gpio) 108*eaaa4f7eSrev13@wp.pl { 109*eaaa4f7eSrev13@wp.pl return gpio % 16; 110*eaaa4f7eSrev13@wp.pl } 111*eaaa4f7eSrev13@wp.pl 112*eaaa4f7eSrev13@wp.pl int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc, 113*eaaa4f7eSrev13@wp.pl const struct stm32_gpio_ctl *gpio_ctl); 114*eaaa4f7eSrev13@wp.pl int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state); 115*eaaa4f7eSrev13@wp.pl 116*eaaa4f7eSrev13@wp.pl #endif /* _STM32_GPIO_H_ */ 117