1*2536f18bSPatrice Chotard /*
2*2536f18bSPatrice Chotard  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
3*2536f18bSPatrice Chotard  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
4*2536f18bSPatrice Chotard  *
5*2536f18bSPatrice Chotard  * SPDX-License-Identifier:	GPL-2.0+
6*2536f18bSPatrice Chotard  */
7*2536f18bSPatrice Chotard 
8*2536f18bSPatrice Chotard #ifndef _ASM_ARCH_STM32F_H
9*2536f18bSPatrice Chotard #define _ASM_ARCH_STM32F_H
10*2536f18bSPatrice Chotard 
11*2536f18bSPatrice Chotard #define STM32_PERIPH_BASE	0x40000000UL
12*2536f18bSPatrice Chotard 
13*2536f18bSPatrice Chotard #define STM32_APB2_PERIPH_BASE	(STM32_PERIPH_BASE + 0x00010000)
14*2536f18bSPatrice Chotard #define STM32_AHB1_PERIPH_BASE	(STM32_PERIPH_BASE + 0x00020000)
15*2536f18bSPatrice Chotard 
16*2536f18bSPatrice Chotard #define STM32_SYSCFG_BASE	(STM32_APB2_PERIPH_BASE + 0x3800)
17*2536f18bSPatrice Chotard #define STM32_FLASH_CNTL_BASE	(STM32_AHB1_PERIPH_BASE + 0x3C00)
18*2536f18bSPatrice Chotard 
19*2536f18bSPatrice Chotard void stm32_flash_latency_cfg(int latency);
20*2536f18bSPatrice Chotard 
21*2536f18bSPatrice Chotard #endif /* _ASM_ARCH_STM32F_H */
22*2536f18bSPatrice Chotard 
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