1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2015, Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
7 #define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__
8 
9 #ifndef __ASSEMBLY__
10 
11 /* MC_ME registers definitions */
12 
13 /* MC_ME_GS */
14 #define MC_ME_GS						(MC_ME_BASE_ADDR + 0x00000000)
15 
16 #define MC_ME_GS_S_SYSCLK_FIRC			(0x0 << 0)
17 #define MC_ME_GS_S_SYSCLK_FXOSC			(0x1 << 0)
18 #define MC_ME_GS_S_SYSCLK_ARMPLL		(0x2 << 0)
19 #define MC_ME_GS_S_STSCLK_DISABLE		(0xF << 0)
20 #define MC_ME_GS_S_FIRC					(1 << 4)
21 #define MC_ME_GS_S_XOSC					(1 << 5)
22 #define MC_ME_GS_S_ARMPLL				(1 << 6)
23 #define MC_ME_GS_S_PERPLL				(1 << 7)
24 #define MC_ME_GS_S_ENETPLL				(1 << 8)
25 #define MC_ME_GS_S_DDRPLL				(1 << 9)
26 #define MC_ME_GS_S_VIDEOPLL				(1 << 10)
27 #define MC_ME_GS_S_MVR					(1 << 20)
28 #define MC_ME_GS_S_PDO					(1 << 23)
29 #define MC_ME_GS_S_MTRANS				(1 << 27)
30 #define MC_ME_GS_S_CRT_MODE_RESET		(0x0 << 28)
31 #define MC_ME_GS_S_CRT_MODE_TEST		(0x1 << 28)
32 #define MC_ME_GS_S_CRT_MODE_DRUN		(0x3 << 28)
33 #define MC_ME_GS_S_CRT_MODE_RUN0		(0x4 << 28)
34 #define MC_ME_GS_S_CRT_MODE_RUN1		(0x5 << 28)
35 #define MC_ME_GS_S_CRT_MODE_RUN2		(0x6 << 28)
36 #define MC_ME_GS_S_CRT_MODE_RUN3		(0x7 << 28)
37 
38 /* MC_ME_MCTL */
39 #define MC_ME_MCTL						(MC_ME_BASE_ADDR + 0x00000004)
40 
41 #define MC_ME_MCTL_KEY					(0x00005AF0)
42 #define MC_ME_MCTL_INVERTEDKEY			(0x0000A50F)
43 #define MC_ME_MCTL_RESET				(0x0 << 28)
44 #define MC_ME_MCTL_TEST					(0x1 << 28)
45 #define MC_ME_MCTL_DRUN					(0x3 << 28)
46 #define MC_ME_MCTL_RUN0					(0x4 << 28)
47 #define MC_ME_MCTL_RUN1					(0x5 << 28)
48 #define MC_ME_MCTL_RUN2					(0x6 << 28)
49 #define MC_ME_MCTL_RUN3					(0x7 << 28)
50 
51 /* MC_ME_ME */
52 #define MC_ME_ME						(MC_ME_BASE_ADDR + 0x00000008)
53 
54 #define MC_ME_ME_RESET_FUNC				(1 << 0)
55 #define MC_ME_ME_TEST					(1 << 1)
56 #define MC_ME_ME_DRUN					(1 << 3)
57 #define MC_ME_ME_RUN0					(1 << 4)
58 #define MC_ME_ME_RUN1					(1 << 5)
59 #define MC_ME_ME_RUN2					(1 << 6)
60 #define MC_ME_ME_RUN3					(1 << 7)
61 
62 /* MC_ME_RUN_PCn */
63 #define MC_ME_RUN_PCn(n)				(MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n))
64 
65 #define MC_ME_RUN_PCn_RESET				(1 << 0)
66 #define MC_ME_RUN_PCn_TEST				(1 << 1)
67 #define MC_ME_RUN_PCn_DRUN				(1 << 3)
68 #define MC_ME_RUN_PCn_RUN0				(1 << 4)
69 #define MC_ME_RUN_PCn_RUN1				(1 << 5)
70 #define MC_ME_RUN_PCn_RUN2				(1 << 6)
71 #define MC_ME_RUN_PCn_RUN3				(1 << 7)
72 
73 /*
74  * MC_ME_RESET_MC/MC_ME_TEST_MC
75  * MC_ME_DRUN_MC
76  * MC_ME_RUNn_MC
77  */
78 #define MC_ME_RESET_MC						(MC_ME_BASE_ADDR + 0x00000020)
79 #define MC_ME_TEST_MC						(MC_ME_BASE_ADDR + 0x00000024)
80 #define MC_ME_DRUN_MC						(MC_ME_BASE_ADDR + 0x0000002C)
81 #define MC_ME_RUNn_MC(n)					(MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n))
82 
83 #define MC_ME_RUNMODE_MC_SYSCLK(val)	(MC_ME_RUNMODE_MC_SYSCLK_MASK & (val))
84 #define MC_ME_RUNMODE_MC_SYSCLK_MASK	(0x0000000F)
85 #define MC_ME_RUNMODE_MC_FIRCON			(1 << 4)
86 #define MC_ME_RUNMODE_MC_XOSCON			(1 << 5)
87 #define MC_ME_RUNMODE_MC_PLL(pll)		(1 << (6 + (pll)))
88 #define MC_ME_RUNMODE_MC_MVRON			(1 << 20)
89 #define MC_ME_RUNMODE_MC_PDO			(1 << 23)
90 #define MC_ME_RUNMODE_MC_PWRLVL0		(1 << 28)
91 #define MC_ME_RUNMODE_MC_PWRLVL1		(1 << 29)
92 #define MC_ME_RUNMODE_MC_PWRLVL2		(1 << 30)
93 
94 /* MC_ME_DRUN_SEC_CC_I */
95 #define MC_ME_DRUN_SEC_CC_I					(MC_ME_BASE_ADDR + 0x260)
96 /* MC_ME_RUNn_SEC_CC_I */
97 #define MC_ME_RUNn_SEC_CC_I(n)				(MC_ME_BASE_ADDR + 0x270 + (n) * 0x10)
98 #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset)	((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset)
99 #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET	(4)
100 #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET	(8)
101 #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET	(12)
102 #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK		(0x3)
103 
104 /*
105  * ME_PCTLn
106  * Please note that these registers are 8 bits width, so
107  * the operations over them should be done using 8 bits operations.
108  */
109 #define MC_ME_PCTLn_RUNPCm(n)			( (n) & MC_ME_PCTLn_RUNPCm_MASK )
110 #define MC_ME_PCTLn_RUNPCm_MASK			(0x7)
111 
112 /* DEC200 Peripheral Control Register		*/
113 #define MC_ME_PCTL39	(MC_ME_BASE_ADDR + 0x000000E4)
114 /* 2D-ACE Peripheral Control Register		*/
115 #define MC_ME_PCTL40	(MC_ME_BASE_ADDR + 0x000000EB)
116 /* ENET Peripheral Control Register		*/
117 #define MC_ME_PCTL50	(MC_ME_BASE_ADDR + 0x000000F1)
118 /* DMACHMUX0 Peripheral Control Register	*/
119 #define MC_ME_PCTL49	(MC_ME_BASE_ADDR + 0x000000F2)
120 /* CSI0 Peripheral Control Register			*/
121 #define MC_ME_PCTL48	(MC_ME_BASE_ADDR + 0x000000F3)
122 /* MMDC0 Peripheral Control Register		*/
123 #define MC_ME_PCTL54	(MC_ME_BASE_ADDR + 0x000000F5)
124 /* FRAY Peripheral Control Register			*/
125 #define MC_ME_PCTL52	(MC_ME_BASE_ADDR + 0x000000F7)
126 /* PIT0 Peripheral Control Register			*/
127 #define MC_ME_PCTL58	(MC_ME_BASE_ADDR + 0x000000F9)
128 /* FlexTIMER0 Peripheral Control Register	*/
129 #define MC_ME_PCTL79	(MC_ME_BASE_ADDR + 0x0000010C)
130 /* SARADC0 Peripheral Control Register		*/
131 #define MC_ME_PCTL77	(MC_ME_BASE_ADDR + 0x0000010E)
132 /* LINFLEX0 Peripheral Control Register		*/
133 #define MC_ME_PCTL83	(MC_ME_BASE_ADDR + 0x00000110)
134 /* IIC0 Peripheral Control Register			*/
135 #define MC_ME_PCTL81	(MC_ME_BASE_ADDR + 0x00000112)
136 /* DSPI0 Peripheral Control Register		*/
137 #define MC_ME_PCTL87	(MC_ME_BASE_ADDR + 0x00000114)
138 /* CANFD0 Peripheral Control Register		*/
139 #define MC_ME_PCTL85	(MC_ME_BASE_ADDR + 0x00000116)
140 /* CRC0 Peripheral Control Register			*/
141 #define MC_ME_PCTL91	(MC_ME_BASE_ADDR + 0x00000118)
142 /* DSPI2 Peripheral Control Register		*/
143 #define MC_ME_PCTL89	(MC_ME_BASE_ADDR + 0x0000011A)
144 /* SDHC Peripheral Control Register			*/
145 #define MC_ME_PCTL93	(MC_ME_BASE_ADDR + 0x0000011E)
146 /* VIU0 Peripheral Control Register			*/
147 #define MC_ME_PCTL100	(MC_ME_BASE_ADDR + 0x00000127)
148 /* HPSMI Peripheral Control Register		*/
149 #define MC_ME_PCTL104	(MC_ME_BASE_ADDR + 0x0000012B)
150 /* SIPI Peripheral Control Register			*/
151 #define MC_ME_PCTL116	(MC_ME_BASE_ADDR + 0x00000137)
152 /* LFAST Peripheral Control Register		*/
153 #define MC_ME_PCTL120	(MC_ME_BASE_ADDR + 0x0000013B)
154 /* MMDC1 Peripheral Control Register		*/
155 #define MC_ME_PCTL162	(MC_ME_BASE_ADDR + 0x00000161)
156 /* DMACHMUX1 Peripheral Control Register	*/
157 #define MC_ME_PCTL161	(MC_ME_BASE_ADDR + 0x00000162)
158 /* CSI1 Peripheral Control Register			*/
159 #define MC_ME_PCTL160	(MC_ME_BASE_ADDR + 0x00000163)
160 /* QUADSPI0 Peripheral Control Register		*/
161 #define MC_ME_PCTL166	(MC_ME_BASE_ADDR + 0x00000165)
162 /* PIT1 Peripheral Control Register			*/
163 #define MC_ME_PCTL170	(MC_ME_BASE_ADDR + 0x00000169)
164 /* FlexTIMER1 Peripheral Control Register	*/
165 #define MC_ME_PCTL182	(MC_ME_BASE_ADDR + 0x00000175)
166 /* IIC2 Peripheral Control Register			*/
167 #define MC_ME_PCTL186	(MC_ME_BASE_ADDR + 0x00000179)
168 /* IIC1 Peripheral Control Register			*/
169 #define MC_ME_PCTL184	(MC_ME_BASE_ADDR + 0x0000017B)
170 /* CANFD1 Peripheral Control Register		*/
171 #define MC_ME_PCTL190	(MC_ME_BASE_ADDR + 0x0000017D)
172 /* LINFLEX1 Peripheral Control Register		*/
173 #define MC_ME_PCTL188	(MC_ME_BASE_ADDR + 0x0000017F)
174 /* DSPI3 Peripheral Control Register		*/
175 #define MC_ME_PCTL194	(MC_ME_BASE_ADDR + 0x00000181)
176 /* DSPI1 Peripheral Control Register		*/
177 #define MC_ME_PCTL192	(MC_ME_BASE_ADDR + 0x00000183)
178 /* TSENS Peripheral Control Register		*/
179 #define MC_ME_PCTL206	(MC_ME_BASE_ADDR + 0x0000018D)
180 /* CRC1 Peripheral Control Register			*/
181 #define MC_ME_PCTL204	(MC_ME_BASE_ADDR + 0x0000018F)
182 /* VIU1 Peripheral Control Register		*/
183 #define MC_ME_PCTL208	(MC_ME_BASE_ADDR + 0x00000193)
184 /* JPEG Peripheral Control Register		*/
185 #define MC_ME_PCTL212	(MC_ME_BASE_ADDR + 0x00000197)
186 /* H264_DEC Peripheral Control Register	*/
187 #define MC_ME_PCTL216	(MC_ME_BASE_ADDR + 0x0000019B)
188 /* H264_ENC Peripheral Control Register	*/
189 #define MC_ME_PCTL220	(MC_ME_BASE_ADDR + 0x0000019F)
190 /* MBIST Peripheral Control Register	*/
191 #define MC_ME_PCTL236	(MC_ME_BASE_ADDR + 0x000001A9)
192 
193 /* Core status register */
194 #define MC_ME_CS               (MC_ME_BASE_ADDR + 0x000001C0)
195 
196 #endif
197 
198 #endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */
199