1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 29702ec00SEddy Petrișor /* 39702ec00SEddy Petrișor * (C) Copyright 2015, Freescale Semiconductor, Inc. 49702ec00SEddy Petrișor */ 59702ec00SEddy Petrișor 69702ec00SEddy Petrișor #ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__ 79702ec00SEddy Petrișor #define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__ 89702ec00SEddy Petrișor 99702ec00SEddy Petrișor #ifndef __ASSEMBLY__ 109702ec00SEddy Petrișor 119702ec00SEddy Petrișor /* MC_ME registers definitions */ 129702ec00SEddy Petrișor 139702ec00SEddy Petrișor /* MC_ME_GS */ 149702ec00SEddy Petrișor #define MC_ME_GS (MC_ME_BASE_ADDR + 0x00000000) 159702ec00SEddy Petrișor 169702ec00SEddy Petrișor #define MC_ME_GS_S_SYSCLK_FIRC (0x0 << 0) 179702ec00SEddy Petrișor #define MC_ME_GS_S_SYSCLK_FXOSC (0x1 << 0) 189702ec00SEddy Petrișor #define MC_ME_GS_S_SYSCLK_ARMPLL (0x2 << 0) 199702ec00SEddy Petrișor #define MC_ME_GS_S_STSCLK_DISABLE (0xF << 0) 209702ec00SEddy Petrișor #define MC_ME_GS_S_FIRC (1 << 4) 219702ec00SEddy Petrișor #define MC_ME_GS_S_XOSC (1 << 5) 229702ec00SEddy Petrișor #define MC_ME_GS_S_ARMPLL (1 << 6) 239702ec00SEddy Petrișor #define MC_ME_GS_S_PERPLL (1 << 7) 249702ec00SEddy Petrișor #define MC_ME_GS_S_ENETPLL (1 << 8) 259702ec00SEddy Petrișor #define MC_ME_GS_S_DDRPLL (1 << 9) 269702ec00SEddy Petrișor #define MC_ME_GS_S_VIDEOPLL (1 << 10) 279702ec00SEddy Petrișor #define MC_ME_GS_S_MVR (1 << 20) 289702ec00SEddy Petrișor #define MC_ME_GS_S_PDO (1 << 23) 299702ec00SEddy Petrișor #define MC_ME_GS_S_MTRANS (1 << 27) 309702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_RESET (0x0 << 28) 319702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_TEST (0x1 << 28) 329702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_DRUN (0x3 << 28) 339702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_RUN0 (0x4 << 28) 349702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_RUN1 (0x5 << 28) 359702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_RUN2 (0x6 << 28) 369702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_RUN3 (0x7 << 28) 379702ec00SEddy Petrișor 389702ec00SEddy Petrișor /* MC_ME_MCTL */ 399702ec00SEddy Petrișor #define MC_ME_MCTL (MC_ME_BASE_ADDR + 0x00000004) 409702ec00SEddy Petrișor 419702ec00SEddy Petrișor #define MC_ME_MCTL_KEY (0x00005AF0) 429702ec00SEddy Petrișor #define MC_ME_MCTL_INVERTEDKEY (0x0000A50F) 439702ec00SEddy Petrișor #define MC_ME_MCTL_RESET (0x0 << 28) 449702ec00SEddy Petrișor #define MC_ME_MCTL_TEST (0x1 << 28) 459702ec00SEddy Petrișor #define MC_ME_MCTL_DRUN (0x3 << 28) 469702ec00SEddy Petrișor #define MC_ME_MCTL_RUN0 (0x4 << 28) 479702ec00SEddy Petrișor #define MC_ME_MCTL_RUN1 (0x5 << 28) 489702ec00SEddy Petrișor #define MC_ME_MCTL_RUN2 (0x6 << 28) 499702ec00SEddy Petrișor #define MC_ME_MCTL_RUN3 (0x7 << 28) 509702ec00SEddy Petrișor 519702ec00SEddy Petrișor /* MC_ME_ME */ 529702ec00SEddy Petrișor #define MC_ME_ME (MC_ME_BASE_ADDR + 0x00000008) 539702ec00SEddy Petrișor 549702ec00SEddy Petrișor #define MC_ME_ME_RESET_FUNC (1 << 0) 559702ec00SEddy Petrișor #define MC_ME_ME_TEST (1 << 1) 569702ec00SEddy Petrișor #define MC_ME_ME_DRUN (1 << 3) 579702ec00SEddy Petrișor #define MC_ME_ME_RUN0 (1 << 4) 589702ec00SEddy Petrișor #define MC_ME_ME_RUN1 (1 << 5) 599702ec00SEddy Petrișor #define MC_ME_ME_RUN2 (1 << 6) 609702ec00SEddy Petrișor #define MC_ME_ME_RUN3 (1 << 7) 619702ec00SEddy Petrișor 629702ec00SEddy Petrișor /* MC_ME_RUN_PCn */ 639702ec00SEddy Petrișor #define MC_ME_RUN_PCn(n) (MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n)) 649702ec00SEddy Petrișor 659702ec00SEddy Petrișor #define MC_ME_RUN_PCn_RESET (1 << 0) 669702ec00SEddy Petrișor #define MC_ME_RUN_PCn_TEST (1 << 1) 679702ec00SEddy Petrișor #define MC_ME_RUN_PCn_DRUN (1 << 3) 689702ec00SEddy Petrișor #define MC_ME_RUN_PCn_RUN0 (1 << 4) 699702ec00SEddy Petrișor #define MC_ME_RUN_PCn_RUN1 (1 << 5) 709702ec00SEddy Petrișor #define MC_ME_RUN_PCn_RUN2 (1 << 6) 719702ec00SEddy Petrișor #define MC_ME_RUN_PCn_RUN3 (1 << 7) 729702ec00SEddy Petrișor 739702ec00SEddy Petrișor /* 749702ec00SEddy Petrișor * MC_ME_RESET_MC/MC_ME_TEST_MC 759702ec00SEddy Petrișor * MC_ME_DRUN_MC 769702ec00SEddy Petrișor * MC_ME_RUNn_MC 779702ec00SEddy Petrișor */ 789702ec00SEddy Petrișor #define MC_ME_RESET_MC (MC_ME_BASE_ADDR + 0x00000020) 799702ec00SEddy Petrișor #define MC_ME_TEST_MC (MC_ME_BASE_ADDR + 0x00000024) 809702ec00SEddy Petrișor #define MC_ME_DRUN_MC (MC_ME_BASE_ADDR + 0x0000002C) 819702ec00SEddy Petrișor #define MC_ME_RUNn_MC(n) (MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n)) 829702ec00SEddy Petrișor 839702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_SYSCLK(val) (MC_ME_RUNMODE_MC_SYSCLK_MASK & (val)) 849702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_SYSCLK_MASK (0x0000000F) 859702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_FIRCON (1 << 4) 869702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_XOSCON (1 << 5) 879702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_PLL(pll) (1 << (6 + (pll))) 889702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_MVRON (1 << 20) 899702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_PDO (1 << 23) 909702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_PWRLVL0 (1 << 28) 919702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_PWRLVL1 (1 << 29) 929702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_PWRLVL2 (1 << 30) 939702ec00SEddy Petrișor 949702ec00SEddy Petrișor /* MC_ME_DRUN_SEC_CC_I */ 959702ec00SEddy Petrișor #define MC_ME_DRUN_SEC_CC_I (MC_ME_BASE_ADDR + 0x260) 969702ec00SEddy Petrișor /* MC_ME_RUNn_SEC_CC_I */ 979702ec00SEddy Petrișor #define MC_ME_RUNn_SEC_CC_I(n) (MC_ME_BASE_ADDR + 0x270 + (n) * 0x10) 989702ec00SEddy Petrișor #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset) ((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset) 999702ec00SEddy Petrișor #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET (4) 1009702ec00SEddy Petrișor #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET (8) 1019702ec00SEddy Petrișor #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET (12) 1029702ec00SEddy Petrișor #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK (0x3) 1039702ec00SEddy Petrișor 1049702ec00SEddy Petrișor /* 1059702ec00SEddy Petrișor * ME_PCTLn 1069702ec00SEddy Petrișor * Please note that these registers are 8 bits width, so 1079702ec00SEddy Petrișor * the operations over them should be done using 8 bits operations. 1089702ec00SEddy Petrișor */ 1099702ec00SEddy Petrișor #define MC_ME_PCTLn_RUNPCm(n) ( (n) & MC_ME_PCTLn_RUNPCm_MASK ) 1109702ec00SEddy Petrișor #define MC_ME_PCTLn_RUNPCm_MASK (0x7) 1119702ec00SEddy Petrișor 1129702ec00SEddy Petrișor /* DEC200 Peripheral Control Register */ 1139702ec00SEddy Petrișor #define MC_ME_PCTL39 (MC_ME_BASE_ADDR + 0x000000E4) 1149702ec00SEddy Petrișor /* 2D-ACE Peripheral Control Register */ 1159702ec00SEddy Petrișor #define MC_ME_PCTL40 (MC_ME_BASE_ADDR + 0x000000EB) 1169702ec00SEddy Petrișor /* ENET Peripheral Control Register */ 1179702ec00SEddy Petrișor #define MC_ME_PCTL50 (MC_ME_BASE_ADDR + 0x000000F1) 1189702ec00SEddy Petrișor /* DMACHMUX0 Peripheral Control Register */ 1199702ec00SEddy Petrișor #define MC_ME_PCTL49 (MC_ME_BASE_ADDR + 0x000000F2) 1209702ec00SEddy Petrișor /* CSI0 Peripheral Control Register */ 1219702ec00SEddy Petrișor #define MC_ME_PCTL48 (MC_ME_BASE_ADDR + 0x000000F3) 1229702ec00SEddy Petrișor /* MMDC0 Peripheral Control Register */ 1239702ec00SEddy Petrișor #define MC_ME_PCTL54 (MC_ME_BASE_ADDR + 0x000000F5) 1249702ec00SEddy Petrișor /* FRAY Peripheral Control Register */ 1259702ec00SEddy Petrișor #define MC_ME_PCTL52 (MC_ME_BASE_ADDR + 0x000000F7) 1269702ec00SEddy Petrișor /* PIT0 Peripheral Control Register */ 1279702ec00SEddy Petrișor #define MC_ME_PCTL58 (MC_ME_BASE_ADDR + 0x000000F9) 1289702ec00SEddy Petrișor /* FlexTIMER0 Peripheral Control Register */ 1299702ec00SEddy Petrișor #define MC_ME_PCTL79 (MC_ME_BASE_ADDR + 0x0000010C) 1309702ec00SEddy Petrișor /* SARADC0 Peripheral Control Register */ 1319702ec00SEddy Petrișor #define MC_ME_PCTL77 (MC_ME_BASE_ADDR + 0x0000010E) 1329702ec00SEddy Petrișor /* LINFLEX0 Peripheral Control Register */ 1339702ec00SEddy Petrișor #define MC_ME_PCTL83 (MC_ME_BASE_ADDR + 0x00000110) 1349702ec00SEddy Petrișor /* IIC0 Peripheral Control Register */ 1359702ec00SEddy Petrișor #define MC_ME_PCTL81 (MC_ME_BASE_ADDR + 0x00000112) 1369702ec00SEddy Petrișor /* DSPI0 Peripheral Control Register */ 1379702ec00SEddy Petrișor #define MC_ME_PCTL87 (MC_ME_BASE_ADDR + 0x00000114) 1389702ec00SEddy Petrișor /* CANFD0 Peripheral Control Register */ 1399702ec00SEddy Petrișor #define MC_ME_PCTL85 (MC_ME_BASE_ADDR + 0x00000116) 1409702ec00SEddy Petrișor /* CRC0 Peripheral Control Register */ 1419702ec00SEddy Petrișor #define MC_ME_PCTL91 (MC_ME_BASE_ADDR + 0x00000118) 1429702ec00SEddy Petrișor /* DSPI2 Peripheral Control Register */ 1439702ec00SEddy Petrișor #define MC_ME_PCTL89 (MC_ME_BASE_ADDR + 0x0000011A) 1449702ec00SEddy Petrișor /* SDHC Peripheral Control Register */ 1459702ec00SEddy Petrișor #define MC_ME_PCTL93 (MC_ME_BASE_ADDR + 0x0000011E) 1469702ec00SEddy Petrișor /* VIU0 Peripheral Control Register */ 1479702ec00SEddy Petrișor #define MC_ME_PCTL100 (MC_ME_BASE_ADDR + 0x00000127) 1489702ec00SEddy Petrișor /* HPSMI Peripheral Control Register */ 1499702ec00SEddy Petrișor #define MC_ME_PCTL104 (MC_ME_BASE_ADDR + 0x0000012B) 1509702ec00SEddy Petrișor /* SIPI Peripheral Control Register */ 1519702ec00SEddy Petrișor #define MC_ME_PCTL116 (MC_ME_BASE_ADDR + 0x00000137) 1529702ec00SEddy Petrișor /* LFAST Peripheral Control Register */ 1539702ec00SEddy Petrișor #define MC_ME_PCTL120 (MC_ME_BASE_ADDR + 0x0000013B) 1549702ec00SEddy Petrișor /* MMDC1 Peripheral Control Register */ 1559702ec00SEddy Petrișor #define MC_ME_PCTL162 (MC_ME_BASE_ADDR + 0x00000161) 1569702ec00SEddy Petrișor /* DMACHMUX1 Peripheral Control Register */ 1579702ec00SEddy Petrișor #define MC_ME_PCTL161 (MC_ME_BASE_ADDR + 0x00000162) 1589702ec00SEddy Petrișor /* CSI1 Peripheral Control Register */ 1599702ec00SEddy Petrișor #define MC_ME_PCTL160 (MC_ME_BASE_ADDR + 0x00000163) 1609702ec00SEddy Petrișor /* QUADSPI0 Peripheral Control Register */ 1619702ec00SEddy Petrișor #define MC_ME_PCTL166 (MC_ME_BASE_ADDR + 0x00000165) 1629702ec00SEddy Petrișor /* PIT1 Peripheral Control Register */ 1639702ec00SEddy Petrișor #define MC_ME_PCTL170 (MC_ME_BASE_ADDR + 0x00000169) 1649702ec00SEddy Petrișor /* FlexTIMER1 Peripheral Control Register */ 1659702ec00SEddy Petrișor #define MC_ME_PCTL182 (MC_ME_BASE_ADDR + 0x00000175) 1669702ec00SEddy Petrișor /* IIC2 Peripheral Control Register */ 1679702ec00SEddy Petrișor #define MC_ME_PCTL186 (MC_ME_BASE_ADDR + 0x00000179) 1689702ec00SEddy Petrișor /* IIC1 Peripheral Control Register */ 1699702ec00SEddy Petrișor #define MC_ME_PCTL184 (MC_ME_BASE_ADDR + 0x0000017B) 1709702ec00SEddy Petrișor /* CANFD1 Peripheral Control Register */ 1719702ec00SEddy Petrișor #define MC_ME_PCTL190 (MC_ME_BASE_ADDR + 0x0000017D) 1729702ec00SEddy Petrișor /* LINFLEX1 Peripheral Control Register */ 1739702ec00SEddy Petrișor #define MC_ME_PCTL188 (MC_ME_BASE_ADDR + 0x0000017F) 1749702ec00SEddy Petrișor /* DSPI3 Peripheral Control Register */ 1759702ec00SEddy Petrișor #define MC_ME_PCTL194 (MC_ME_BASE_ADDR + 0x00000181) 1769702ec00SEddy Petrișor /* DSPI1 Peripheral Control Register */ 1779702ec00SEddy Petrișor #define MC_ME_PCTL192 (MC_ME_BASE_ADDR + 0x00000183) 1789702ec00SEddy Petrișor /* TSENS Peripheral Control Register */ 1799702ec00SEddy Petrișor #define MC_ME_PCTL206 (MC_ME_BASE_ADDR + 0x0000018D) 1809702ec00SEddy Petrișor /* CRC1 Peripheral Control Register */ 1819702ec00SEddy Petrișor #define MC_ME_PCTL204 (MC_ME_BASE_ADDR + 0x0000018F) 1829702ec00SEddy Petrișor /* VIU1 Peripheral Control Register */ 1839702ec00SEddy Petrișor #define MC_ME_PCTL208 (MC_ME_BASE_ADDR + 0x00000193) 1849702ec00SEddy Petrișor /* JPEG Peripheral Control Register */ 1859702ec00SEddy Petrișor #define MC_ME_PCTL212 (MC_ME_BASE_ADDR + 0x00000197) 1869702ec00SEddy Petrișor /* H264_DEC Peripheral Control Register */ 1879702ec00SEddy Petrișor #define MC_ME_PCTL216 (MC_ME_BASE_ADDR + 0x0000019B) 1889702ec00SEddy Petrișor /* H264_ENC Peripheral Control Register */ 1899702ec00SEddy Petrișor #define MC_ME_PCTL220 (MC_ME_BASE_ADDR + 0x0000019F) 1909702ec00SEddy Petrișor /* MBIST Peripheral Control Register */ 1919702ec00SEddy Petrișor #define MC_ME_PCTL236 (MC_ME_BASE_ADDR + 0x000001A9) 1929702ec00SEddy Petrișor 1939702ec00SEddy Petrișor /* Core status register */ 1949702ec00SEddy Petrișor #define MC_ME_CS (MC_ME_BASE_ADDR + 0x000001C0) 1959702ec00SEddy Petrișor 1969702ec00SEddy Petrișor #endif 1979702ec00SEddy Petrișor 1989702ec00SEddy Petrișor #endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */ 199