1*9702ec00SEddy Petrișor /* 2*9702ec00SEddy Petrișor * (C) Copyright 2015, Freescale Semiconductor, Inc. 3*9702ec00SEddy Petrișor * 4*9702ec00SEddy Petrișor * SPDX-License-Identifier: GPL-2.0+ 5*9702ec00SEddy Petrișor */ 6*9702ec00SEddy Petrișor 7*9702ec00SEddy Petrișor #ifndef __ARCH_ARM_MACH_S32V234_MCME_REGS_H__ 8*9702ec00SEddy Petrișor #define __ARCH_ARM_MACH_S32V234_MCME_REGS_H__ 9*9702ec00SEddy Petrișor 10*9702ec00SEddy Petrișor #ifndef __ASSEMBLY__ 11*9702ec00SEddy Petrișor 12*9702ec00SEddy Petrișor /* MC_ME registers definitions */ 13*9702ec00SEddy Petrișor 14*9702ec00SEddy Petrișor /* MC_ME_GS */ 15*9702ec00SEddy Petrișor #define MC_ME_GS (MC_ME_BASE_ADDR + 0x00000000) 16*9702ec00SEddy Petrișor 17*9702ec00SEddy Petrișor #define MC_ME_GS_S_SYSCLK_FIRC (0x0 << 0) 18*9702ec00SEddy Petrișor #define MC_ME_GS_S_SYSCLK_FXOSC (0x1 << 0) 19*9702ec00SEddy Petrișor #define MC_ME_GS_S_SYSCLK_ARMPLL (0x2 << 0) 20*9702ec00SEddy Petrișor #define MC_ME_GS_S_STSCLK_DISABLE (0xF << 0) 21*9702ec00SEddy Petrișor #define MC_ME_GS_S_FIRC (1 << 4) 22*9702ec00SEddy Petrișor #define MC_ME_GS_S_XOSC (1 << 5) 23*9702ec00SEddy Petrișor #define MC_ME_GS_S_ARMPLL (1 << 6) 24*9702ec00SEddy Petrișor #define MC_ME_GS_S_PERPLL (1 << 7) 25*9702ec00SEddy Petrișor #define MC_ME_GS_S_ENETPLL (1 << 8) 26*9702ec00SEddy Petrișor #define MC_ME_GS_S_DDRPLL (1 << 9) 27*9702ec00SEddy Petrișor #define MC_ME_GS_S_VIDEOPLL (1 << 10) 28*9702ec00SEddy Petrișor #define MC_ME_GS_S_MVR (1 << 20) 29*9702ec00SEddy Petrișor #define MC_ME_GS_S_PDO (1 << 23) 30*9702ec00SEddy Petrișor #define MC_ME_GS_S_MTRANS (1 << 27) 31*9702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_RESET (0x0 << 28) 32*9702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_TEST (0x1 << 28) 33*9702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_DRUN (0x3 << 28) 34*9702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_RUN0 (0x4 << 28) 35*9702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_RUN1 (0x5 << 28) 36*9702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_RUN2 (0x6 << 28) 37*9702ec00SEddy Petrișor #define MC_ME_GS_S_CRT_MODE_RUN3 (0x7 << 28) 38*9702ec00SEddy Petrișor 39*9702ec00SEddy Petrișor /* MC_ME_MCTL */ 40*9702ec00SEddy Petrișor #define MC_ME_MCTL (MC_ME_BASE_ADDR + 0x00000004) 41*9702ec00SEddy Petrișor 42*9702ec00SEddy Petrișor #define MC_ME_MCTL_KEY (0x00005AF0) 43*9702ec00SEddy Petrișor #define MC_ME_MCTL_INVERTEDKEY (0x0000A50F) 44*9702ec00SEddy Petrișor #define MC_ME_MCTL_RESET (0x0 << 28) 45*9702ec00SEddy Petrișor #define MC_ME_MCTL_TEST (0x1 << 28) 46*9702ec00SEddy Petrișor #define MC_ME_MCTL_DRUN (0x3 << 28) 47*9702ec00SEddy Petrișor #define MC_ME_MCTL_RUN0 (0x4 << 28) 48*9702ec00SEddy Petrișor #define MC_ME_MCTL_RUN1 (0x5 << 28) 49*9702ec00SEddy Petrișor #define MC_ME_MCTL_RUN2 (0x6 << 28) 50*9702ec00SEddy Petrișor #define MC_ME_MCTL_RUN3 (0x7 << 28) 51*9702ec00SEddy Petrișor 52*9702ec00SEddy Petrișor /* MC_ME_ME */ 53*9702ec00SEddy Petrișor #define MC_ME_ME (MC_ME_BASE_ADDR + 0x00000008) 54*9702ec00SEddy Petrișor 55*9702ec00SEddy Petrișor #define MC_ME_ME_RESET_FUNC (1 << 0) 56*9702ec00SEddy Petrișor #define MC_ME_ME_TEST (1 << 1) 57*9702ec00SEddy Petrișor #define MC_ME_ME_DRUN (1 << 3) 58*9702ec00SEddy Petrișor #define MC_ME_ME_RUN0 (1 << 4) 59*9702ec00SEddy Petrișor #define MC_ME_ME_RUN1 (1 << 5) 60*9702ec00SEddy Petrișor #define MC_ME_ME_RUN2 (1 << 6) 61*9702ec00SEddy Petrișor #define MC_ME_ME_RUN3 (1 << 7) 62*9702ec00SEddy Petrișor 63*9702ec00SEddy Petrișor /* MC_ME_RUN_PCn */ 64*9702ec00SEddy Petrișor #define MC_ME_RUN_PCn(n) (MC_ME_BASE_ADDR + 0x00000080 + 0x4 * (n)) 65*9702ec00SEddy Petrișor 66*9702ec00SEddy Petrișor #define MC_ME_RUN_PCn_RESET (1 << 0) 67*9702ec00SEddy Petrișor #define MC_ME_RUN_PCn_TEST (1 << 1) 68*9702ec00SEddy Petrișor #define MC_ME_RUN_PCn_DRUN (1 << 3) 69*9702ec00SEddy Petrișor #define MC_ME_RUN_PCn_RUN0 (1 << 4) 70*9702ec00SEddy Petrișor #define MC_ME_RUN_PCn_RUN1 (1 << 5) 71*9702ec00SEddy Petrișor #define MC_ME_RUN_PCn_RUN2 (1 << 6) 72*9702ec00SEddy Petrișor #define MC_ME_RUN_PCn_RUN3 (1 << 7) 73*9702ec00SEddy Petrișor 74*9702ec00SEddy Petrișor /* 75*9702ec00SEddy Petrișor * MC_ME_RESET_MC/MC_ME_TEST_MC 76*9702ec00SEddy Petrișor * MC_ME_DRUN_MC 77*9702ec00SEddy Petrișor * MC_ME_RUNn_MC 78*9702ec00SEddy Petrișor */ 79*9702ec00SEddy Petrișor #define MC_ME_RESET_MC (MC_ME_BASE_ADDR + 0x00000020) 80*9702ec00SEddy Petrișor #define MC_ME_TEST_MC (MC_ME_BASE_ADDR + 0x00000024) 81*9702ec00SEddy Petrișor #define MC_ME_DRUN_MC (MC_ME_BASE_ADDR + 0x0000002C) 82*9702ec00SEddy Petrișor #define MC_ME_RUNn_MC(n) (MC_ME_BASE_ADDR + 0x00000030 + 0x4 * (n)) 83*9702ec00SEddy Petrișor 84*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_SYSCLK(val) (MC_ME_RUNMODE_MC_SYSCLK_MASK & (val)) 85*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_SYSCLK_MASK (0x0000000F) 86*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_FIRCON (1 << 4) 87*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_XOSCON (1 << 5) 88*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_PLL(pll) (1 << (6 + (pll))) 89*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_MVRON (1 << 20) 90*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_PDO (1 << 23) 91*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_PWRLVL0 (1 << 28) 92*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_PWRLVL1 (1 << 29) 93*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_MC_PWRLVL2 (1 << 30) 94*9702ec00SEddy Petrișor 95*9702ec00SEddy Petrișor /* MC_ME_DRUN_SEC_CC_I */ 96*9702ec00SEddy Petrișor #define MC_ME_DRUN_SEC_CC_I (MC_ME_BASE_ADDR + 0x260) 97*9702ec00SEddy Petrișor /* MC_ME_RUNn_SEC_CC_I */ 98*9702ec00SEddy Petrișor #define MC_ME_RUNn_SEC_CC_I(n) (MC_ME_BASE_ADDR + 0x270 + (n) * 0x10) 99*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK(val,offset) ((MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK & (val)) << offset) 100*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK1_OFFSET (4) 101*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK2_OFFSET (8) 102*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK3_OFFSET (12) 103*9702ec00SEddy Petrișor #define MC_ME_RUNMODE_SEC_CC_I_SYSCLK_MASK (0x3) 104*9702ec00SEddy Petrișor 105*9702ec00SEddy Petrișor /* 106*9702ec00SEddy Petrișor * ME_PCTLn 107*9702ec00SEddy Petrișor * Please note that these registers are 8 bits width, so 108*9702ec00SEddy Petrișor * the operations over them should be done using 8 bits operations. 109*9702ec00SEddy Petrișor */ 110*9702ec00SEddy Petrișor #define MC_ME_PCTLn_RUNPCm(n) ( (n) & MC_ME_PCTLn_RUNPCm_MASK ) 111*9702ec00SEddy Petrișor #define MC_ME_PCTLn_RUNPCm_MASK (0x7) 112*9702ec00SEddy Petrișor 113*9702ec00SEddy Petrișor /* DEC200 Peripheral Control Register */ 114*9702ec00SEddy Petrișor #define MC_ME_PCTL39 (MC_ME_BASE_ADDR + 0x000000E4) 115*9702ec00SEddy Petrișor /* 2D-ACE Peripheral Control Register */ 116*9702ec00SEddy Petrișor #define MC_ME_PCTL40 (MC_ME_BASE_ADDR + 0x000000EB) 117*9702ec00SEddy Petrișor /* ENET Peripheral Control Register */ 118*9702ec00SEddy Petrișor #define MC_ME_PCTL50 (MC_ME_BASE_ADDR + 0x000000F1) 119*9702ec00SEddy Petrișor /* DMACHMUX0 Peripheral Control Register */ 120*9702ec00SEddy Petrișor #define MC_ME_PCTL49 (MC_ME_BASE_ADDR + 0x000000F2) 121*9702ec00SEddy Petrișor /* CSI0 Peripheral Control Register */ 122*9702ec00SEddy Petrișor #define MC_ME_PCTL48 (MC_ME_BASE_ADDR + 0x000000F3) 123*9702ec00SEddy Petrișor /* MMDC0 Peripheral Control Register */ 124*9702ec00SEddy Petrișor #define MC_ME_PCTL54 (MC_ME_BASE_ADDR + 0x000000F5) 125*9702ec00SEddy Petrișor /* FRAY Peripheral Control Register */ 126*9702ec00SEddy Petrișor #define MC_ME_PCTL52 (MC_ME_BASE_ADDR + 0x000000F7) 127*9702ec00SEddy Petrișor /* PIT0 Peripheral Control Register */ 128*9702ec00SEddy Petrișor #define MC_ME_PCTL58 (MC_ME_BASE_ADDR + 0x000000F9) 129*9702ec00SEddy Petrișor /* FlexTIMER0 Peripheral Control Register */ 130*9702ec00SEddy Petrișor #define MC_ME_PCTL79 (MC_ME_BASE_ADDR + 0x0000010C) 131*9702ec00SEddy Petrișor /* SARADC0 Peripheral Control Register */ 132*9702ec00SEddy Petrișor #define MC_ME_PCTL77 (MC_ME_BASE_ADDR + 0x0000010E) 133*9702ec00SEddy Petrișor /* LINFLEX0 Peripheral Control Register */ 134*9702ec00SEddy Petrișor #define MC_ME_PCTL83 (MC_ME_BASE_ADDR + 0x00000110) 135*9702ec00SEddy Petrișor /* IIC0 Peripheral Control Register */ 136*9702ec00SEddy Petrișor #define MC_ME_PCTL81 (MC_ME_BASE_ADDR + 0x00000112) 137*9702ec00SEddy Petrișor /* DSPI0 Peripheral Control Register */ 138*9702ec00SEddy Petrișor #define MC_ME_PCTL87 (MC_ME_BASE_ADDR + 0x00000114) 139*9702ec00SEddy Petrișor /* CANFD0 Peripheral Control Register */ 140*9702ec00SEddy Petrișor #define MC_ME_PCTL85 (MC_ME_BASE_ADDR + 0x00000116) 141*9702ec00SEddy Petrișor /* CRC0 Peripheral Control Register */ 142*9702ec00SEddy Petrișor #define MC_ME_PCTL91 (MC_ME_BASE_ADDR + 0x00000118) 143*9702ec00SEddy Petrișor /* DSPI2 Peripheral Control Register */ 144*9702ec00SEddy Petrișor #define MC_ME_PCTL89 (MC_ME_BASE_ADDR + 0x0000011A) 145*9702ec00SEddy Petrișor /* SDHC Peripheral Control Register */ 146*9702ec00SEddy Petrișor #define MC_ME_PCTL93 (MC_ME_BASE_ADDR + 0x0000011E) 147*9702ec00SEddy Petrișor /* VIU0 Peripheral Control Register */ 148*9702ec00SEddy Petrișor #define MC_ME_PCTL100 (MC_ME_BASE_ADDR + 0x00000127) 149*9702ec00SEddy Petrișor /* HPSMI Peripheral Control Register */ 150*9702ec00SEddy Petrișor #define MC_ME_PCTL104 (MC_ME_BASE_ADDR + 0x0000012B) 151*9702ec00SEddy Petrișor /* SIPI Peripheral Control Register */ 152*9702ec00SEddy Petrișor #define MC_ME_PCTL116 (MC_ME_BASE_ADDR + 0x00000137) 153*9702ec00SEddy Petrișor /* LFAST Peripheral Control Register */ 154*9702ec00SEddy Petrișor #define MC_ME_PCTL120 (MC_ME_BASE_ADDR + 0x0000013B) 155*9702ec00SEddy Petrișor /* MMDC1 Peripheral Control Register */ 156*9702ec00SEddy Petrișor #define MC_ME_PCTL162 (MC_ME_BASE_ADDR + 0x00000161) 157*9702ec00SEddy Petrișor /* DMACHMUX1 Peripheral Control Register */ 158*9702ec00SEddy Petrișor #define MC_ME_PCTL161 (MC_ME_BASE_ADDR + 0x00000162) 159*9702ec00SEddy Petrișor /* CSI1 Peripheral Control Register */ 160*9702ec00SEddy Petrișor #define MC_ME_PCTL160 (MC_ME_BASE_ADDR + 0x00000163) 161*9702ec00SEddy Petrișor /* QUADSPI0 Peripheral Control Register */ 162*9702ec00SEddy Petrișor #define MC_ME_PCTL166 (MC_ME_BASE_ADDR + 0x00000165) 163*9702ec00SEddy Petrișor /* PIT1 Peripheral Control Register */ 164*9702ec00SEddy Petrișor #define MC_ME_PCTL170 (MC_ME_BASE_ADDR + 0x00000169) 165*9702ec00SEddy Petrișor /* FlexTIMER1 Peripheral Control Register */ 166*9702ec00SEddy Petrișor #define MC_ME_PCTL182 (MC_ME_BASE_ADDR + 0x00000175) 167*9702ec00SEddy Petrișor /* IIC2 Peripheral Control Register */ 168*9702ec00SEddy Petrișor #define MC_ME_PCTL186 (MC_ME_BASE_ADDR + 0x00000179) 169*9702ec00SEddy Petrișor /* IIC1 Peripheral Control Register */ 170*9702ec00SEddy Petrișor #define MC_ME_PCTL184 (MC_ME_BASE_ADDR + 0x0000017B) 171*9702ec00SEddy Petrișor /* CANFD1 Peripheral Control Register */ 172*9702ec00SEddy Petrișor #define MC_ME_PCTL190 (MC_ME_BASE_ADDR + 0x0000017D) 173*9702ec00SEddy Petrișor /* LINFLEX1 Peripheral Control Register */ 174*9702ec00SEddy Petrișor #define MC_ME_PCTL188 (MC_ME_BASE_ADDR + 0x0000017F) 175*9702ec00SEddy Petrișor /* DSPI3 Peripheral Control Register */ 176*9702ec00SEddy Petrișor #define MC_ME_PCTL194 (MC_ME_BASE_ADDR + 0x00000181) 177*9702ec00SEddy Petrișor /* DSPI1 Peripheral Control Register */ 178*9702ec00SEddy Petrișor #define MC_ME_PCTL192 (MC_ME_BASE_ADDR + 0x00000183) 179*9702ec00SEddy Petrișor /* TSENS Peripheral Control Register */ 180*9702ec00SEddy Petrișor #define MC_ME_PCTL206 (MC_ME_BASE_ADDR + 0x0000018D) 181*9702ec00SEddy Petrișor /* CRC1 Peripheral Control Register */ 182*9702ec00SEddy Petrișor #define MC_ME_PCTL204 (MC_ME_BASE_ADDR + 0x0000018F) 183*9702ec00SEddy Petrișor /* VIU1 Peripheral Control Register */ 184*9702ec00SEddy Petrișor #define MC_ME_PCTL208 (MC_ME_BASE_ADDR + 0x00000193) 185*9702ec00SEddy Petrișor /* JPEG Peripheral Control Register */ 186*9702ec00SEddy Petrișor #define MC_ME_PCTL212 (MC_ME_BASE_ADDR + 0x00000197) 187*9702ec00SEddy Petrișor /* H264_DEC Peripheral Control Register */ 188*9702ec00SEddy Petrișor #define MC_ME_PCTL216 (MC_ME_BASE_ADDR + 0x0000019B) 189*9702ec00SEddy Petrișor /* H264_ENC Peripheral Control Register */ 190*9702ec00SEddy Petrișor #define MC_ME_PCTL220 (MC_ME_BASE_ADDR + 0x0000019F) 191*9702ec00SEddy Petrișor /* MBIST Peripheral Control Register */ 192*9702ec00SEddy Petrișor #define MC_ME_PCTL236 (MC_ME_BASE_ADDR + 0x000001A9) 193*9702ec00SEddy Petrișor 194*9702ec00SEddy Petrișor /* Core status register */ 195*9702ec00SEddy Petrișor #define MC_ME_CS (MC_ME_BASE_ADDR + 0x000001C0) 196*9702ec00SEddy Petrișor 197*9702ec00SEddy Petrișor #endif 198*9702ec00SEddy Petrișor 199*9702ec00SEddy Petrișor #endif /*__ARCH_ARM_MACH_S32V234_MCME_REGS_H__ */ 200