1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2015, Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
7 #define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
8 
9 #ifndef __ASSEMBLY__
10 
11 /* MC_CGM registers definitions */
12 /* MC_CGM_SC_SS */
13 #define CGM_SC_SS(cgm_addr)			( ((cgm_addr) + 0x000007E4) )
14 #define MC_CGM_SC_SEL_FIRC			(0x0)
15 #define MC_CGM_SC_SEL_XOSC			(0x1)
16 #define MC_CGM_SC_SEL_ARMPLL		(0x2)
17 #define MC_CGM_SC_SEL_CLKDISABLE	(0xF)
18 
19 /* MC_CGM_SC_DCn */
20 #define CGM_SC_DCn(cgm_addr,dc)		( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) )
21 #define MC_CGM_SC_DCn_PREDIV(val)	(MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET))
22 #define MC_CGM_SC_DCn_PREDIV_MASK	(0x00070000)
23 #define MC_CGM_SC_DCn_PREDIV_OFFSET	(16)
24 #define MC_CGM_SC_DCn_DE			(1 << 31)
25 #define MC_CGM_SC_SEL_MASK			(0x0F000000)
26 #define MC_CGM_SC_SEL_OFFSET		(24)
27 
28 /* MC_CGM_ACn_DCm */
29 #define CGM_ACn_DCm(cgm_addr,ac,dc)		( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) )
30 #define MC_CGM_ACn_DCm_PREDIV(val)		(MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET))
31 
32 /*
33  * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown
34  * that the 5th bit is always ignored during writes if the current
35  * MC_CGM_ACn_DCm_PREDIV field has only 4 bits
36  *
37  * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits
38  *
39  * This should be changed if any problems occur.
40  */
41 #define MC_CGM_ACn_DCm_PREDIV_MASK		(0x001F0000)
42 #define MC_CGM_ACn_DCm_PREDIV_OFFSET	(16)
43 #define MC_CGM_ACn_DCm_DE				(1 << 31)
44 
45 /*
46  * MC_CGM_ACn_SC/MC_CGM_ACn_SS
47  */
48 #define CGM_ACn_SC(cgm_addr,ac)			((cgm_addr + 0x00000800) + ((ac) * 0x20))
49 #define CGM_ACn_SS(cgm_addr,ac)			((cgm_addr + 0x00000804) + ((ac) * 0x20))
50 #define MC_CGM_ACn_SEL_MASK				(0x07000000)
51 #define MC_CGM_ACn_SEL_SET(source)		(MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET))
52 #define MC_CGM_ACn_SEL_OFFSET			(24)
53 
54 #define MC_CGM_ACn_SEL_FIRC				(0x0)
55 #define MC_CGM_ACn_SEL_XOSC				(0x1)
56 #define MC_CGM_ACn_SEL_ARMPLL			(0x2)
57 /*
58  * According to the manual some PLL can be divided by X (X={1,3,5}):
59  * PERPLLDIVX, VIDEOPLLDIVX.
60  */
61 #define MC_CGM_ACn_SEL_PERPLLDIVX		(0x3)
62 #define MC_CGM_ACn_SEL_ENETPLL			(0x4)
63 #define MC_CGM_ACn_SEL_DDRPLL			(0x5)
64 #define MC_CGM_ACn_SEL_EXTSRCPAD		(0x7)
65 #define MC_CGM_ACn_SEL_SYSCLK			(0x8)
66 #define MC_CGM_ACn_SEL_VIDEOPLLDIVX		(0x9)
67 #define MC_CGM_ACn_SEL_PERCLK			(0xA)
68 
69 /* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */
70 #define PLLDIG_PLLDV(pll)				((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80))
71 #define PLLDIG_PLLDV_MFD(div)			(PLLDIG_PLLDV_MFD_MASK & (div))
72 #define PLLDIG_PLLDV_MFD_MASK			(0x000000FF)
73 
74 /*
75  * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to
76  * the reference manual. This other value respect the formula 2^[RFDPHIBY+1]
77  */
78 #define PLLDIG_PLLDV_RFDPHI_SET(val)	(PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET))
79 #define PLLDIG_PLLDV_RFDPHI_MASK		(0x003F0000)
80 #define PLLDIG_PLLDV_RFDPHI_MAXVALUE	(0x3F)
81 #define PLLDIG_PLLDV_RFDPHI_OFFSET		(16)
82 
83 #define PLLDIG_PLLDV_RFDPHI1_SET(val)	(PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET))
84 #define PLLDIG_PLLDV_RFDPHI1_MASK		(0x7E000000)
85 #define PLLDIG_PLLDV_RFDPHI1_MAXVALUE	(0x3F)
86 #define PLLDIG_PLLDV_RFDPHI1_OFFSET		(25)
87 
88 #define PLLDIG_PLLDV_PREDIV_SET(val)	(PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET))
89 #define PLLDIG_PLLDV_PREDIV_MASK		(0x00007000)
90 #define PLLDIG_PLLDV_PREDIV_MAXVALUE	(0x7)
91 #define PLLDIG_PLLDV_PREDIV_OFFSET		(12)
92 
93 /* PLLDIG PLL Fractional  Divide Register (PLLDIG_PLLFD) */
94 #define PLLDIG_PLLFD(pll)				((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80))
95 #define PLLDIG_PLLFD_MFN_SET(val)		(PLLDIG_PLLFD_MFN_MASK & (val))
96 #define PLLDIG_PLLFD_MFN_MASK			(0x00007FFF)
97 #define PLLDIG_PLLFD_SMDEN				(1 << 30)
98 
99 /* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */
100 #define PLLDIG_PLLCAL1(pll)				((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80))
101 #define PLLDIG_PLLCAL1_NDAC1_SET(val)	(PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET))
102 #define PLLDIG_PLLCAL1_NDAC1_OFFSET		(24)
103 #define PLLDIG_PLLCAL1_NDAC1_MASK		(0x7F000000)
104 
105 /* Digital Frequency Synthesizer (DFS) */
106 /* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */
107 #define DFS0_BASE_ADDR				(MC_CGM0_BASE_ADDR + 0x00000040)
108 
109 /* DFS DLL Program Register 1 */
110 #define DFS_DLLPRG1(pll)			(DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80))
111 
112 #define DFS_DLLPRG1_V2IGC_SET(val)	(DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET))
113 #define DFS_DLLPRG1_V2IGC_OFFSET	(0)
114 #define DFS_DLLPRG1_V2IGC_MASK		(0x00000007)
115 
116 #define DFS_DLLPRG1_LCKWT_SET(val)		(DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET))
117 #define DFS_DLLPRG1_LCKWT_OFFSET		(4)
118 #define DFS_DLLPRG1_LCKWT_MASK			(0x00000030)
119 
120 #define DFS_DLLPRG1_DACIN_SET(val)		(DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET))
121 #define DFS_DLLPRG1_DACIN_OFFSET		(6)
122 #define DFS_DLLPRG1_DACIN_MASK			(0x000001C0)
123 
124 #define DFS_DLLPRG1_CALBYPEN_SET(val)	(DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET))
125 #define DFS_DLLPRG1_CALBYPEN_OFFSET		(9)
126 #define DFS_DLLPRG1_CALBYPEN_MASK		(0x00000200)
127 
128 #define DFS_DLLPRG1_VSETTLCTRL_SET(val)	(DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET))
129 #define DFS_DLLPRG1_VSETTLCTRL_OFFSET	(10)
130 #define DFS_DLLPRG1_VSETTLCTRL_MASK		(0x00000C00)
131 
132 #define DFS_DLLPRG1_CPICTRL_SET(val)	(DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET))
133 #define DFS_DLLPRG1_CPICTRL_OFFSET		(12)
134 #define DFS_DLLPRG1_CPICTRL_MASK		(0x00007000)
135 
136 /* DFS Control Register (DFS_CTRL) */
137 #define DFS_CTRL(pll)					(DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80))
138 #define DFS_CTRL_DLL_LOLIE				(1 << 0)
139 #define DFS_CTRL_DLL_RESET				(1 << 1)
140 
141 /* DFS Port Status Register (DFS_PORTSR) */
142 #define DFS_PORTSR(pll)						(DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80))
143 /* DFS Port Reset Register (DFS_PORTRESET) */
144 #define DFS_PORTRESET(pll)					(DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80))
145 #define DFS_PORTRESET_PORTRESET_SET(val)	(DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET))
146 #define DFS_PORTRESET_PORTRESET_MAXVAL		(0xF)
147 #define DFS_PORTRESET_PORTRESET_MASK		(0x0000000F)
148 #define DFS_PORTRESET_PORTRESET_OFFSET		(0)
149 
150 /* DFS Divide Register Portn (DFS_DVPORTn) */
151 #define DFS_DVPORTn(pll,n)			(DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4)))
152 
153 /*
154  * The mathematical formula for fdfs_clockout is the following:
155  * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) )
156  */
157 #define DFS_DVPORTn_MFI_SET(val)	(DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) )
158 #define DFS_DVPORTn_MFN_SET(val)	(DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) )
159 #define DFS_DVPORTn_MFI_MASK		(0x0000FF00)
160 #define DFS_DVPORTn_MFN_MASK		(0x000000FF)
161 #define DFS_DVPORTn_MFI_MAXVAL		(0xFF)
162 #define DFS_DVPORTn_MFN_MAXVAL		(0xFF)
163 #define DFS_DVPORTn_MFI_OFFSET		(8)
164 #define DFS_DVPORTn_MFN_OFFSET		(0)
165 #define DFS_MAXNUMBER				(4)
166 
167 #define DFS_PARAMS_Nr				(3)
168 
169 /* Frequencies are in Hz */
170 #define FIRC_CLK_FREQ				(48000000)
171 #define XOSC_CLK_FREQ				(40000000)
172 
173 #define PLL_MIN_FREQ				(650000000)
174 #define PLL_MAX_FREQ				(1300000000)
175 
176 #define ARM_PLL_PHI0_FREQ			(1000000000)
177 #define ARM_PLL_PHI1_FREQ			(1000000000)
178 /* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
179 #define ARM_PLL_PHI1_DFS1_EN		(1)
180 #define ARM_PLL_PHI1_DFS1_MFI		(3)
181 #define ARM_PLL_PHI1_DFS1_MFN		(194)
182 /* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
183 #define ARM_PLL_PHI1_DFS2_EN		(1)
184 #define ARM_PLL_PHI1_DFS2_MFI		(1)
185 #define ARM_PLL_PHI1_DFS2_MFN		(170)
186 /* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
187 #define ARM_PLL_PHI1_DFS3_EN		(1)
188 #define ARM_PLL_PHI1_DFS3_MFI		(1)
189 #define ARM_PLL_PHI1_DFS3_MFN		(170)
190 #define ARM_PLL_PHI1_DFS_Nr			(3)
191 #define ARM_PLL_PLLDV_PREDIV		(2)
192 #define ARM_PLL_PLLDV_MFD			(50)
193 #define ARM_PLL_PLLDV_MFN			(0)
194 
195 #define PERIPH_PLL_PHI0_FREQ		(400000000)
196 #define PERIPH_PLL_PHI1_FREQ		(100000000)
197 #define PERIPH_PLL_PHI1_DFS_Nr		(0)
198 #define PERIPH_PLL_PLLDV_PREDIV		(1)
199 #define PERIPH_PLL_PLLDV_MFD		(30)
200 #define PERIPH_PLL_PLLDV_MFN		(0)
201 
202 #define ENET_PLL_PHI0_FREQ			(500000000)
203 #define ENET_PLL_PHI1_FREQ			(1000000000)
204 /* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
205 #define ENET_PLL_PHI1_DFS1_EN		(1)
206 #define ENET_PLL_PHI1_DFS1_MFI		(2)
207 #define ENET_PLL_PHI1_DFS1_MFN		(219)
208 /* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
209 #define ENET_PLL_PHI1_DFS2_EN		(1)
210 #define ENET_PLL_PHI1_DFS2_MFI		(2)
211 #define ENET_PLL_PHI1_DFS2_MFN		(219)
212 /* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
213 #define ENET_PLL_PHI1_DFS3_EN		(1)
214 #define ENET_PLL_PHI1_DFS3_MFI		(3)
215 #define ENET_PLL_PHI1_DFS3_MFN		(32)
216 /* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
217 #define ENET_PLL_PHI1_DFS4_EN		(1)
218 #define ENET_PLL_PHI1_DFS4_MFI		(2)
219 #define ENET_PLL_PHI1_DFS4_MFN		(0)
220 #define ENET_PLL_PHI1_DFS_Nr		(4)
221 #define ENET_PLL_PLLDV_PREDIV		(2)
222 #define ENET_PLL_PLLDV_MFD			(50)
223 #define ENET_PLL_PLLDV_MFN			(0)
224 
225 #define DDR_PLL_PHI0_FREQ			(533000000)
226 #define DDR_PLL_PHI1_FREQ			(1066000000)
227 /* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
228 #define DDR_PLL_PHI1_DFS1_EN		(1)
229 #define DDR_PLL_PHI1_DFS1_MFI		(2)
230 #define DDR_PLL_PHI1_DFS1_MFN		(33)
231 /* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */
232 #define DDR_PLL_PHI1_DFS2_EN		(1)
233 #define DDR_PLL_PHI1_DFS2_MFI		(2)
234 #define DDR_PLL_PHI1_DFS2_MFN		(33)
235 /* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */
236 #define DDR_PLL_PHI1_DFS3_EN		(1)
237 #define DDR_PLL_PHI1_DFS3_MFI		(3)
238 #define DDR_PLL_PHI1_DFS3_MFN		(11)
239 #define DDR_PLL_PHI1_DFS_Nr			(3)
240 #define DDR_PLL_PLLDV_PREDIV		(2)
241 #define DDR_PLL_PLLDV_MFD			(53)
242 #define DDR_PLL_PLLDV_MFN			(6144)
243 
244 #define VIDEO_PLL_PHI0_FREQ			(600000000)
245 #define VIDEO_PLL_PHI1_FREQ			(0)
246 #define VIDEO_PLL_PHI1_DFS_Nr		(0)
247 #define VIDEO_PLL_PLLDV_PREDIV		(1)
248 #define VIDEO_PLL_PLLDV_MFD			(30)
249 #define VIDEO_PLL_PLLDV_MFN			(0)
250 
251 #endif
252 
253 #endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */
254