1 /*
2  * (C) Copyright 2015, Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
8 #define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__
9 
10 #ifndef __ASSEMBLY__
11 
12 /* MC_CGM registers definitions */
13 /* MC_CGM_SC_SS */
14 #define CGM_SC_SS(cgm_addr)			( ((cgm_addr) + 0x000007E4) )
15 #define MC_CGM_SC_SEL_FIRC			(0x0)
16 #define MC_CGM_SC_SEL_XOSC			(0x1)
17 #define MC_CGM_SC_SEL_ARMPLL		(0x2)
18 #define MC_CGM_SC_SEL_CLKDISABLE	(0xF)
19 
20 /* MC_CGM_SC_DCn */
21 #define CGM_SC_DCn(cgm_addr,dc)		( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) )
22 #define MC_CGM_SC_DCn_PREDIV(val)	(MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET))
23 #define MC_CGM_SC_DCn_PREDIV_MASK	(0x00070000)
24 #define MC_CGM_SC_DCn_PREDIV_OFFSET	(16)
25 #define MC_CGM_SC_DCn_DE			(1 << 31)
26 #define MC_CGM_SC_SEL_MASK			(0x0F000000)
27 #define MC_CGM_SC_SEL_OFFSET		(24)
28 
29 /* MC_CGM_ACn_DCm */
30 #define CGM_ACn_DCm(cgm_addr,ac,dc)		( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) )
31 #define MC_CGM_ACn_DCm_PREDIV(val)		(MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET))
32 
33 /*
34  * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown
35  * that the 5th bit is always ignored during writes if the current
36  * MC_CGM_ACn_DCm_PREDIV field has only 4 bits
37  *
38  * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits
39  *
40  * This should be changed if any problems occur.
41  */
42 #define MC_CGM_ACn_DCm_PREDIV_MASK		(0x001F0000)
43 #define MC_CGM_ACn_DCm_PREDIV_OFFSET	(16)
44 #define MC_CGM_ACn_DCm_DE				(1 << 31)
45 
46 /*
47  * MC_CGM_ACn_SC/MC_CGM_ACn_SS
48  */
49 #define CGM_ACn_SC(cgm_addr,ac)			((cgm_addr + 0x00000800) + ((ac) * 0x20))
50 #define CGM_ACn_SS(cgm_addr,ac)			((cgm_addr + 0x00000804) + ((ac) * 0x20))
51 #define MC_CGM_ACn_SEL_MASK				(0x07000000)
52 #define MC_CGM_ACn_SEL_SET(source)		(MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET))
53 #define MC_CGM_ACn_SEL_OFFSET			(24)
54 
55 #define MC_CGM_ACn_SEL_FIRC				(0x0)
56 #define MC_CGM_ACn_SEL_XOSC				(0x1)
57 #define MC_CGM_ACn_SEL_ARMPLL			(0x2)
58 /*
59  * According to the manual some PLL can be divided by X (X={1,3,5}):
60  * PERPLLDIVX, VIDEOPLLDIVX.
61  */
62 #define MC_CGM_ACn_SEL_PERPLLDIVX		(0x3)
63 #define MC_CGM_ACn_SEL_ENETPLL			(0x4)
64 #define MC_CGM_ACn_SEL_DDRPLL			(0x5)
65 #define MC_CGM_ACn_SEL_EXTSRCPAD		(0x7)
66 #define MC_CGM_ACn_SEL_SYSCLK			(0x8)
67 #define MC_CGM_ACn_SEL_VIDEOPLLDIVX		(0x9)
68 #define MC_CGM_ACn_SEL_PERCLK			(0xA)
69 
70 /* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */
71 #define PLLDIG_PLLDV(pll)				((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80))
72 #define PLLDIG_PLLDV_MFD(div)			(PLLDIG_PLLDV_MFD_MASK & (div))
73 #define PLLDIG_PLLDV_MFD_MASK			(0x000000FF)
74 
75 /*
76  * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to
77  * the reference manual. This other value respect the formula 2^[RFDPHIBY+1]
78  */
79 #define PLLDIG_PLLDV_RFDPHI_SET(val)	(PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET))
80 #define PLLDIG_PLLDV_RFDPHI_MASK		(0x003F0000)
81 #define PLLDIG_PLLDV_RFDPHI_MAXVALUE	(0x3F)
82 #define PLLDIG_PLLDV_RFDPHI_OFFSET		(16)
83 
84 #define PLLDIG_PLLDV_RFDPHI1_SET(val)	(PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET))
85 #define PLLDIG_PLLDV_RFDPHI1_MASK		(0x7E000000)
86 #define PLLDIG_PLLDV_RFDPHI1_MAXVALUE	(0x3F)
87 #define PLLDIG_PLLDV_RFDPHI1_OFFSET		(25)
88 
89 #define PLLDIG_PLLDV_PREDIV_SET(val)	(PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET))
90 #define PLLDIG_PLLDV_PREDIV_MASK		(0x00007000)
91 #define PLLDIG_PLLDV_PREDIV_MAXVALUE	(0x7)
92 #define PLLDIG_PLLDV_PREDIV_OFFSET		(12)
93 
94 /* PLLDIG PLL Fractional  Divide Register (PLLDIG_PLLFD) */
95 #define PLLDIG_PLLFD(pll)				((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80))
96 #define PLLDIG_PLLFD_MFN_SET(val)		(PLLDIG_PLLFD_MFN_MASK & (val))
97 #define PLLDIG_PLLFD_MFN_MASK			(0x00007FFF)
98 #define PLLDIG_PLLFD_SMDEN				(1 << 30)
99 
100 /* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */
101 #define PLLDIG_PLLCAL1(pll)				((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80))
102 #define PLLDIG_PLLCAL1_NDAC1_SET(val)	(PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET))
103 #define PLLDIG_PLLCAL1_NDAC1_OFFSET		(24)
104 #define PLLDIG_PLLCAL1_NDAC1_MASK		(0x7F000000)
105 
106 /* Digital Frequency Synthesizer (DFS) */
107 /* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */
108 #define DFS0_BASE_ADDR				(MC_CGM0_BASE_ADDR + 0x00000040)
109 
110 /* DFS DLL Program Register 1 */
111 #define DFS_DLLPRG1(pll)			(DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80))
112 
113 #define DFS_DLLPRG1_V2IGC_SET(val)	(DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET))
114 #define DFS_DLLPRG1_V2IGC_OFFSET	(0)
115 #define DFS_DLLPRG1_V2IGC_MASK		(0x00000007)
116 
117 #define DFS_DLLPRG1_LCKWT_SET(val)		(DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET))
118 #define DFS_DLLPRG1_LCKWT_OFFSET		(4)
119 #define DFS_DLLPRG1_LCKWT_MASK			(0x00000030)
120 
121 #define DFS_DLLPRG1_DACIN_SET(val)		(DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET))
122 #define DFS_DLLPRG1_DACIN_OFFSET		(6)
123 #define DFS_DLLPRG1_DACIN_MASK			(0x000001C0)
124 
125 #define DFS_DLLPRG1_CALBYPEN_SET(val)	(DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET))
126 #define DFS_DLLPRG1_CALBYPEN_OFFSET		(9)
127 #define DFS_DLLPRG1_CALBYPEN_MASK		(0x00000200)
128 
129 #define DFS_DLLPRG1_VSETTLCTRL_SET(val)	(DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET))
130 #define DFS_DLLPRG1_VSETTLCTRL_OFFSET	(10)
131 #define DFS_DLLPRG1_VSETTLCTRL_MASK		(0x00000C00)
132 
133 #define DFS_DLLPRG1_CPICTRL_SET(val)	(DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET))
134 #define DFS_DLLPRG1_CPICTRL_OFFSET		(12)
135 #define DFS_DLLPRG1_CPICTRL_MASK		(0x00007000)
136 
137 /* DFS Control Register (DFS_CTRL) */
138 #define DFS_CTRL(pll)					(DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80))
139 #define DFS_CTRL_DLL_LOLIE				(1 << 0)
140 #define DFS_CTRL_DLL_RESET				(1 << 1)
141 
142 /* DFS Port Status Register (DFS_PORTSR) */
143 #define DFS_PORTSR(pll)						(DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80))
144 /* DFS Port Reset Register (DFS_PORTRESET) */
145 #define DFS_PORTRESET(pll)					(DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80))
146 #define DFS_PORTRESET_PORTRESET_SET(val)	(DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET))
147 #define DFS_PORTRESET_PORTRESET_MAXVAL		(0xF)
148 #define DFS_PORTRESET_PORTRESET_MASK		(0x0000000F)
149 #define DFS_PORTRESET_PORTRESET_OFFSET		(0)
150 
151 /* DFS Divide Register Portn (DFS_DVPORTn) */
152 #define DFS_DVPORTn(pll,n)			(DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4)))
153 
154 /*
155  * The mathematical formula for fdfs_clockout is the following:
156  * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) )
157  */
158 #define DFS_DVPORTn_MFI_SET(val)	(DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) )
159 #define DFS_DVPORTn_MFN_SET(val)	(DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) )
160 #define DFS_DVPORTn_MFI_MASK		(0x0000FF00)
161 #define DFS_DVPORTn_MFN_MASK		(0x000000FF)
162 #define DFS_DVPORTn_MFI_MAXVAL		(0xFF)
163 #define DFS_DVPORTn_MFN_MAXVAL		(0xFF)
164 #define DFS_DVPORTn_MFI_OFFSET		(8)
165 #define DFS_DVPORTn_MFN_OFFSET		(0)
166 #define DFS_MAXNUMBER				(4)
167 
168 #define DFS_PARAMS_Nr				(3)
169 
170 /* Frequencies are in Hz */
171 #define FIRC_CLK_FREQ				(48000000)
172 #define XOSC_CLK_FREQ				(40000000)
173 
174 #define PLL_MIN_FREQ				(650000000)
175 #define PLL_MAX_FREQ				(1300000000)
176 
177 #define ARM_PLL_PHI0_FREQ			(1000000000)
178 #define ARM_PLL_PHI1_FREQ			(1000000000)
179 /* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
180 #define ARM_PLL_PHI1_DFS1_EN		(1)
181 #define ARM_PLL_PHI1_DFS1_MFI		(3)
182 #define ARM_PLL_PHI1_DFS1_MFN		(194)
183 /* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
184 #define ARM_PLL_PHI1_DFS2_EN		(1)
185 #define ARM_PLL_PHI1_DFS2_MFI		(1)
186 #define ARM_PLL_PHI1_DFS2_MFN		(170)
187 /* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
188 #define ARM_PLL_PHI1_DFS3_EN		(1)
189 #define ARM_PLL_PHI1_DFS3_MFI		(1)
190 #define ARM_PLL_PHI1_DFS3_MFN		(170)
191 #define ARM_PLL_PHI1_DFS_Nr			(3)
192 #define ARM_PLL_PLLDV_PREDIV		(2)
193 #define ARM_PLL_PLLDV_MFD			(50)
194 #define ARM_PLL_PLLDV_MFN			(0)
195 
196 #define PERIPH_PLL_PHI0_FREQ		(400000000)
197 #define PERIPH_PLL_PHI1_FREQ		(100000000)
198 #define PERIPH_PLL_PHI1_DFS_Nr		(0)
199 #define PERIPH_PLL_PLLDV_PREDIV		(1)
200 #define PERIPH_PLL_PLLDV_MFD		(30)
201 #define PERIPH_PLL_PLLDV_MFN		(0)
202 
203 #define ENET_PLL_PHI0_FREQ			(500000000)
204 #define ENET_PLL_PHI1_FREQ			(1000000000)
205 /* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
206 #define ENET_PLL_PHI1_DFS1_EN		(1)
207 #define ENET_PLL_PHI1_DFS1_MFI		(2)
208 #define ENET_PLL_PHI1_DFS1_MFN		(219)
209 /* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
210 #define ENET_PLL_PHI1_DFS2_EN		(1)
211 #define ENET_PLL_PHI1_DFS2_MFI		(2)
212 #define ENET_PLL_PHI1_DFS2_MFN		(219)
213 /* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
214 #define ENET_PLL_PHI1_DFS3_EN		(1)
215 #define ENET_PLL_PHI1_DFS3_MFI		(3)
216 #define ENET_PLL_PHI1_DFS3_MFN		(32)
217 /* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
218 #define ENET_PLL_PHI1_DFS4_EN		(1)
219 #define ENET_PLL_PHI1_DFS4_MFI		(2)
220 #define ENET_PLL_PHI1_DFS4_MFN		(0)
221 #define ENET_PLL_PHI1_DFS_Nr		(4)
222 #define ENET_PLL_PLLDV_PREDIV		(2)
223 #define ENET_PLL_PLLDV_MFD			(50)
224 #define ENET_PLL_PLLDV_MFN			(0)
225 
226 #define DDR_PLL_PHI0_FREQ			(533000000)
227 #define DDR_PLL_PHI1_FREQ			(1066000000)
228 /* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
229 #define DDR_PLL_PHI1_DFS1_EN		(1)
230 #define DDR_PLL_PHI1_DFS1_MFI		(2)
231 #define DDR_PLL_PHI1_DFS1_MFN		(33)
232 /* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */
233 #define DDR_PLL_PHI1_DFS2_EN		(1)
234 #define DDR_PLL_PHI1_DFS2_MFI		(2)
235 #define DDR_PLL_PHI1_DFS2_MFN		(33)
236 /* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */
237 #define DDR_PLL_PHI1_DFS3_EN		(1)
238 #define DDR_PLL_PHI1_DFS3_MFI		(3)
239 #define DDR_PLL_PHI1_DFS3_MFN		(11)
240 #define DDR_PLL_PHI1_DFS_Nr			(3)
241 #define DDR_PLL_PLLDV_PREDIV		(2)
242 #define DDR_PLL_PLLDV_MFD			(53)
243 #define DDR_PLL_PLLDV_MFN			(6144)
244 
245 #define VIDEO_PLL_PHI0_FREQ			(600000000)
246 #define VIDEO_PLL_PHI1_FREQ			(0)
247 #define VIDEO_PLL_PHI1_DFS_Nr		(0)
248 #define VIDEO_PLL_PLLDV_PREDIV		(1)
249 #define VIDEO_PLL_PLLDV_MFD			(30)
250 #define VIDEO_PLL_PLLDV_MFN			(0)
251 
252 #endif
253 
254 #endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */
255