1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 29702ec00SEddy Petrișor /* 39702ec00SEddy Petrișor * (C) Copyright 2015, Freescale Semiconductor, Inc. 49702ec00SEddy Petrișor */ 59702ec00SEddy Petrișor 69702ec00SEddy Petrișor #ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ 79702ec00SEddy Petrișor #define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ 89702ec00SEddy Petrișor 99702ec00SEddy Petrișor #ifndef __ASSEMBLY__ 109702ec00SEddy Petrișor 119702ec00SEddy Petrișor /* MC_CGM registers definitions */ 129702ec00SEddy Petrișor /* MC_CGM_SC_SS */ 139702ec00SEddy Petrișor #define CGM_SC_SS(cgm_addr) ( ((cgm_addr) + 0x000007E4) ) 149702ec00SEddy Petrișor #define MC_CGM_SC_SEL_FIRC (0x0) 159702ec00SEddy Petrișor #define MC_CGM_SC_SEL_XOSC (0x1) 169702ec00SEddy Petrișor #define MC_CGM_SC_SEL_ARMPLL (0x2) 179702ec00SEddy Petrișor #define MC_CGM_SC_SEL_CLKDISABLE (0xF) 189702ec00SEddy Petrișor 199702ec00SEddy Petrișor /* MC_CGM_SC_DCn */ 209702ec00SEddy Petrișor #define CGM_SC_DCn(cgm_addr,dc) ( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) ) 219702ec00SEddy Petrișor #define MC_CGM_SC_DCn_PREDIV(val) (MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET)) 229702ec00SEddy Petrișor #define MC_CGM_SC_DCn_PREDIV_MASK (0x00070000) 239702ec00SEddy Petrișor #define MC_CGM_SC_DCn_PREDIV_OFFSET (16) 249702ec00SEddy Petrișor #define MC_CGM_SC_DCn_DE (1 << 31) 259702ec00SEddy Petrișor #define MC_CGM_SC_SEL_MASK (0x0F000000) 269702ec00SEddy Petrișor #define MC_CGM_SC_SEL_OFFSET (24) 279702ec00SEddy Petrișor 289702ec00SEddy Petrișor /* MC_CGM_ACn_DCm */ 299702ec00SEddy Petrișor #define CGM_ACn_DCm(cgm_addr,ac,dc) ( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) ) 309702ec00SEddy Petrișor #define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET)) 319702ec00SEddy Petrișor 329702ec00SEddy Petrișor /* 339702ec00SEddy Petrișor * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown 349702ec00SEddy Petrișor * that the 5th bit is always ignored during writes if the current 359702ec00SEddy Petrișor * MC_CGM_ACn_DCm_PREDIV field has only 4 bits 369702ec00SEddy Petrișor * 379702ec00SEddy Petrișor * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits 389702ec00SEddy Petrișor * 399702ec00SEddy Petrișor * This should be changed if any problems occur. 409702ec00SEddy Petrișor */ 419702ec00SEddy Petrișor #define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000) 429702ec00SEddy Petrișor #define MC_CGM_ACn_DCm_PREDIV_OFFSET (16) 439702ec00SEddy Petrișor #define MC_CGM_ACn_DCm_DE (1 << 31) 449702ec00SEddy Petrișor 459702ec00SEddy Petrișor /* 469702ec00SEddy Petrișor * MC_CGM_ACn_SC/MC_CGM_ACn_SS 479702ec00SEddy Petrișor */ 489702ec00SEddy Petrișor #define CGM_ACn_SC(cgm_addr,ac) ((cgm_addr + 0x00000800) + ((ac) * 0x20)) 499702ec00SEddy Petrișor #define CGM_ACn_SS(cgm_addr,ac) ((cgm_addr + 0x00000804) + ((ac) * 0x20)) 509702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_MASK (0x07000000) 519702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET)) 529702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_OFFSET (24) 539702ec00SEddy Petrișor 549702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_FIRC (0x0) 559702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_XOSC (0x1) 569702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_ARMPLL (0x2) 579702ec00SEddy Petrișor /* 589702ec00SEddy Petrișor * According to the manual some PLL can be divided by X (X={1,3,5}): 599702ec00SEddy Petrișor * PERPLLDIVX, VIDEOPLLDIVX. 609702ec00SEddy Petrișor */ 619702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_PERPLLDIVX (0x3) 629702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_ENETPLL (0x4) 639702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_DDRPLL (0x5) 649702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_EXTSRCPAD (0x7) 659702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_SYSCLK (0x8) 669702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_VIDEOPLLDIVX (0x9) 679702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_PERCLK (0xA) 689702ec00SEddy Petrișor 699702ec00SEddy Petrișor /* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */ 709702ec00SEddy Petrișor #define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80)) 719702ec00SEddy Petrișor #define PLLDIG_PLLDV_MFD(div) (PLLDIG_PLLDV_MFD_MASK & (div)) 729702ec00SEddy Petrișor #define PLLDIG_PLLDV_MFD_MASK (0x000000FF) 739702ec00SEddy Petrișor 749702ec00SEddy Petrișor /* 759702ec00SEddy Petrișor * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to 769702ec00SEddy Petrișor * the reference manual. This other value respect the formula 2^[RFDPHIBY+1] 779702ec00SEddy Petrișor */ 789702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET)) 799702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI_MASK (0x003F0000) 809702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI_MAXVALUE (0x3F) 819702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI_OFFSET (16) 829702ec00SEddy Petrișor 839702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET)) 849702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI1_MASK (0x7E000000) 859702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI1_MAXVALUE (0x3F) 869702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI1_OFFSET (25) 879702ec00SEddy Petrișor 889702ec00SEddy Petrișor #define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET)) 899702ec00SEddy Petrișor #define PLLDIG_PLLDV_PREDIV_MASK (0x00007000) 909702ec00SEddy Petrișor #define PLLDIG_PLLDV_PREDIV_MAXVALUE (0x7) 919702ec00SEddy Petrișor #define PLLDIG_PLLDV_PREDIV_OFFSET (12) 929702ec00SEddy Petrișor 939702ec00SEddy Petrișor /* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */ 949702ec00SEddy Petrișor #define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80)) 959702ec00SEddy Petrișor #define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val)) 969702ec00SEddy Petrișor #define PLLDIG_PLLFD_MFN_MASK (0x00007FFF) 979702ec00SEddy Petrișor #define PLLDIG_PLLFD_SMDEN (1 << 30) 989702ec00SEddy Petrișor 999702ec00SEddy Petrișor /* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */ 1009702ec00SEddy Petrișor #define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80)) 1019702ec00SEddy Petrișor #define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET)) 1029702ec00SEddy Petrișor #define PLLDIG_PLLCAL1_NDAC1_OFFSET (24) 1039702ec00SEddy Petrișor #define PLLDIG_PLLCAL1_NDAC1_MASK (0x7F000000) 1049702ec00SEddy Petrișor 1059702ec00SEddy Petrișor /* Digital Frequency Synthesizer (DFS) */ 1069702ec00SEddy Petrișor /* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */ 1079702ec00SEddy Petrișor #define DFS0_BASE_ADDR (MC_CGM0_BASE_ADDR + 0x00000040) 1089702ec00SEddy Petrișor 1099702ec00SEddy Petrișor /* DFS DLL Program Register 1 */ 1109702ec00SEddy Petrișor #define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80)) 1119702ec00SEddy Petrișor 1129702ec00SEddy Petrișor #define DFS_DLLPRG1_V2IGC_SET(val) (DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET)) 1139702ec00SEddy Petrișor #define DFS_DLLPRG1_V2IGC_OFFSET (0) 1149702ec00SEddy Petrișor #define DFS_DLLPRG1_V2IGC_MASK (0x00000007) 1159702ec00SEddy Petrișor 1169702ec00SEddy Petrișor #define DFS_DLLPRG1_LCKWT_SET(val) (DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET)) 1179702ec00SEddy Petrișor #define DFS_DLLPRG1_LCKWT_OFFSET (4) 1189702ec00SEddy Petrișor #define DFS_DLLPRG1_LCKWT_MASK (0x00000030) 1199702ec00SEddy Petrișor 1209702ec00SEddy Petrișor #define DFS_DLLPRG1_DACIN_SET(val) (DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET)) 1219702ec00SEddy Petrișor #define DFS_DLLPRG1_DACIN_OFFSET (6) 1229702ec00SEddy Petrișor #define DFS_DLLPRG1_DACIN_MASK (0x000001C0) 1239702ec00SEddy Petrișor 1249702ec00SEddy Petrișor #define DFS_DLLPRG1_CALBYPEN_SET(val) (DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET)) 1259702ec00SEddy Petrișor #define DFS_DLLPRG1_CALBYPEN_OFFSET (9) 1269702ec00SEddy Petrișor #define DFS_DLLPRG1_CALBYPEN_MASK (0x00000200) 1279702ec00SEddy Petrișor 1289702ec00SEddy Petrișor #define DFS_DLLPRG1_VSETTLCTRL_SET(val) (DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET)) 1299702ec00SEddy Petrișor #define DFS_DLLPRG1_VSETTLCTRL_OFFSET (10) 1309702ec00SEddy Petrișor #define DFS_DLLPRG1_VSETTLCTRL_MASK (0x00000C00) 1319702ec00SEddy Petrișor 1329702ec00SEddy Petrișor #define DFS_DLLPRG1_CPICTRL_SET(val) (DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET)) 1339702ec00SEddy Petrișor #define DFS_DLLPRG1_CPICTRL_OFFSET (12) 1349702ec00SEddy Petrișor #define DFS_DLLPRG1_CPICTRL_MASK (0x00007000) 1359702ec00SEddy Petrișor 1369702ec00SEddy Petrișor /* DFS Control Register (DFS_CTRL) */ 1379702ec00SEddy Petrișor #define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80)) 1389702ec00SEddy Petrișor #define DFS_CTRL_DLL_LOLIE (1 << 0) 1399702ec00SEddy Petrișor #define DFS_CTRL_DLL_RESET (1 << 1) 1409702ec00SEddy Petrișor 1419702ec00SEddy Petrișor /* DFS Port Status Register (DFS_PORTSR) */ 1429702ec00SEddy Petrișor #define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80)) 1439702ec00SEddy Petrișor /* DFS Port Reset Register (DFS_PORTRESET) */ 1449702ec00SEddy Petrișor #define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80)) 1459702ec00SEddy Petrișor #define DFS_PORTRESET_PORTRESET_SET(val) (DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET)) 1469702ec00SEddy Petrișor #define DFS_PORTRESET_PORTRESET_MAXVAL (0xF) 1479702ec00SEddy Petrișor #define DFS_PORTRESET_PORTRESET_MASK (0x0000000F) 1489702ec00SEddy Petrișor #define DFS_PORTRESET_PORTRESET_OFFSET (0) 1499702ec00SEddy Petrișor 1509702ec00SEddy Petrișor /* DFS Divide Register Portn (DFS_DVPORTn) */ 1519702ec00SEddy Petrișor #define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4))) 1529702ec00SEddy Petrișor 1539702ec00SEddy Petrișor /* 1549702ec00SEddy Petrișor * The mathematical formula for fdfs_clockout is the following: 1559702ec00SEddy Petrișor * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) ) 1569702ec00SEddy Petrișor */ 1579702ec00SEddy Petrișor #define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) ) 1589702ec00SEddy Petrișor #define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) ) 1599702ec00SEddy Petrișor #define DFS_DVPORTn_MFI_MASK (0x0000FF00) 1609702ec00SEddy Petrișor #define DFS_DVPORTn_MFN_MASK (0x000000FF) 1619702ec00SEddy Petrișor #define DFS_DVPORTn_MFI_MAXVAL (0xFF) 1629702ec00SEddy Petrișor #define DFS_DVPORTn_MFN_MAXVAL (0xFF) 1639702ec00SEddy Petrișor #define DFS_DVPORTn_MFI_OFFSET (8) 1649702ec00SEddy Petrișor #define DFS_DVPORTn_MFN_OFFSET (0) 1659702ec00SEddy Petrișor #define DFS_MAXNUMBER (4) 1669702ec00SEddy Petrișor 1679702ec00SEddy Petrișor #define DFS_PARAMS_Nr (3) 1689702ec00SEddy Petrișor 1699702ec00SEddy Petrișor /* Frequencies are in Hz */ 1709702ec00SEddy Petrișor #define FIRC_CLK_FREQ (48000000) 1719702ec00SEddy Petrișor #define XOSC_CLK_FREQ (40000000) 1729702ec00SEddy Petrișor 1739702ec00SEddy Petrișor #define PLL_MIN_FREQ (650000000) 1749702ec00SEddy Petrișor #define PLL_MAX_FREQ (1300000000) 1759702ec00SEddy Petrișor 1769702ec00SEddy Petrișor #define ARM_PLL_PHI0_FREQ (1000000000) 1779702ec00SEddy Petrișor #define ARM_PLL_PHI1_FREQ (1000000000) 1789702ec00SEddy Petrișor /* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */ 1799702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS1_EN (1) 1809702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS1_MFI (3) 1819702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS1_MFN (194) 1829702ec00SEddy Petrișor /* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */ 1839702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS2_EN (1) 1849702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS2_MFI (1) 1859702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS2_MFN (170) 1869702ec00SEddy Petrișor /* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */ 1879702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS3_EN (1) 1889702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS3_MFI (1) 1899702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS3_MFN (170) 1909702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS_Nr (3) 1919702ec00SEddy Petrișor #define ARM_PLL_PLLDV_PREDIV (2) 1929702ec00SEddy Petrișor #define ARM_PLL_PLLDV_MFD (50) 1939702ec00SEddy Petrișor #define ARM_PLL_PLLDV_MFN (0) 1949702ec00SEddy Petrișor 1959702ec00SEddy Petrișor #define PERIPH_PLL_PHI0_FREQ (400000000) 1969702ec00SEddy Petrișor #define PERIPH_PLL_PHI1_FREQ (100000000) 1979702ec00SEddy Petrișor #define PERIPH_PLL_PHI1_DFS_Nr (0) 1989702ec00SEddy Petrișor #define PERIPH_PLL_PLLDV_PREDIV (1) 1999702ec00SEddy Petrișor #define PERIPH_PLL_PLLDV_MFD (30) 2009702ec00SEddy Petrișor #define PERIPH_PLL_PLLDV_MFN (0) 2019702ec00SEddy Petrișor 2029702ec00SEddy Petrișor #define ENET_PLL_PHI0_FREQ (500000000) 2039702ec00SEddy Petrișor #define ENET_PLL_PHI1_FREQ (1000000000) 2049702ec00SEddy Petrișor /* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/ 2059702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS1_EN (1) 2069702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS1_MFI (2) 2079702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS1_MFN (219) 2089702ec00SEddy Petrișor /* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/ 2099702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS2_EN (1) 2109702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS2_MFI (2) 2119702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS2_MFN (219) 2129702ec00SEddy Petrișor /* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/ 2139702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS3_EN (1) 2149702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS3_MFI (3) 2159702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS3_MFN (32) 2169702ec00SEddy Petrișor /* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/ 2179702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS4_EN (1) 2189702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS4_MFI (2) 2199702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS4_MFN (0) 2209702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS_Nr (4) 2219702ec00SEddy Petrișor #define ENET_PLL_PLLDV_PREDIV (2) 2229702ec00SEddy Petrișor #define ENET_PLL_PLLDV_MFD (50) 2239702ec00SEddy Petrișor #define ENET_PLL_PLLDV_MFN (0) 2249702ec00SEddy Petrișor 2259702ec00SEddy Petrișor #define DDR_PLL_PHI0_FREQ (533000000) 2269702ec00SEddy Petrișor #define DDR_PLL_PHI1_FREQ (1066000000) 2279702ec00SEddy Petrișor /* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */ 2289702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS1_EN (1) 2299702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS1_MFI (2) 2309702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS1_MFN (33) 2319702ec00SEddy Petrișor /* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */ 2329702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS2_EN (1) 2339702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS2_MFI (2) 2349702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS2_MFN (33) 2359702ec00SEddy Petrișor /* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */ 2369702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS3_EN (1) 2379702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS3_MFI (3) 2389702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS3_MFN (11) 2399702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS_Nr (3) 2409702ec00SEddy Petrișor #define DDR_PLL_PLLDV_PREDIV (2) 2419702ec00SEddy Petrișor #define DDR_PLL_PLLDV_MFD (53) 2429702ec00SEddy Petrișor #define DDR_PLL_PLLDV_MFN (6144) 2439702ec00SEddy Petrișor 2449702ec00SEddy Petrișor #define VIDEO_PLL_PHI0_FREQ (600000000) 2459702ec00SEddy Petrișor #define VIDEO_PLL_PHI1_FREQ (0) 2469702ec00SEddy Petrișor #define VIDEO_PLL_PHI1_DFS_Nr (0) 2479702ec00SEddy Petrișor #define VIDEO_PLL_PLLDV_PREDIV (1) 2489702ec00SEddy Petrișor #define VIDEO_PLL_PLLDV_MFD (30) 2499702ec00SEddy Petrișor #define VIDEO_PLL_PLLDV_MFN (0) 2509702ec00SEddy Petrișor 2519702ec00SEddy Petrișor #endif 2529702ec00SEddy Petrișor 2539702ec00SEddy Petrișor #endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */ 254