1*9702ec00SEddy Petrișor /* 2*9702ec00SEddy Petrișor * (C) Copyright 2015, Freescale Semiconductor, Inc. 3*9702ec00SEddy Petrișor * 4*9702ec00SEddy Petrișor * SPDX-License-Identifier: GPL-2.0+ 5*9702ec00SEddy Petrișor */ 6*9702ec00SEddy Petrișor 7*9702ec00SEddy Petrișor #ifndef __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ 8*9702ec00SEddy Petrișor #define __ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ 9*9702ec00SEddy Petrișor 10*9702ec00SEddy Petrișor #ifndef __ASSEMBLY__ 11*9702ec00SEddy Petrișor 12*9702ec00SEddy Petrișor /* MC_CGM registers definitions */ 13*9702ec00SEddy Petrișor /* MC_CGM_SC_SS */ 14*9702ec00SEddy Petrișor #define CGM_SC_SS(cgm_addr) ( ((cgm_addr) + 0x000007E4) ) 15*9702ec00SEddy Petrișor #define MC_CGM_SC_SEL_FIRC (0x0) 16*9702ec00SEddy Petrișor #define MC_CGM_SC_SEL_XOSC (0x1) 17*9702ec00SEddy Petrișor #define MC_CGM_SC_SEL_ARMPLL (0x2) 18*9702ec00SEddy Petrișor #define MC_CGM_SC_SEL_CLKDISABLE (0xF) 19*9702ec00SEddy Petrișor 20*9702ec00SEddy Petrișor /* MC_CGM_SC_DCn */ 21*9702ec00SEddy Petrișor #define CGM_SC_DCn(cgm_addr,dc) ( ((cgm_addr) + 0x000007E8) + ((dc) * 0x4) ) 22*9702ec00SEddy Petrișor #define MC_CGM_SC_DCn_PREDIV(val) (MC_CGM_SC_DCn_PREDIV_MASK & ((val) << MC_CGM_SC_DCn_PREDIV_OFFSET)) 23*9702ec00SEddy Petrișor #define MC_CGM_SC_DCn_PREDIV_MASK (0x00070000) 24*9702ec00SEddy Petrișor #define MC_CGM_SC_DCn_PREDIV_OFFSET (16) 25*9702ec00SEddy Petrișor #define MC_CGM_SC_DCn_DE (1 << 31) 26*9702ec00SEddy Petrișor #define MC_CGM_SC_SEL_MASK (0x0F000000) 27*9702ec00SEddy Petrișor #define MC_CGM_SC_SEL_OFFSET (24) 28*9702ec00SEddy Petrișor 29*9702ec00SEddy Petrișor /* MC_CGM_ACn_DCm */ 30*9702ec00SEddy Petrișor #define CGM_ACn_DCm(cgm_addr,ac,dc) ( ((cgm_addr) + 0x00000808) + ((ac) * 0x20) + ((dc) * 0x4) ) 31*9702ec00SEddy Petrișor #define MC_CGM_ACn_DCm_PREDIV(val) (MC_CGM_ACn_DCm_PREDIV_MASK & ((val) << MC_CGM_ACn_DCm_PREDIV_OFFSET)) 32*9702ec00SEddy Petrișor 33*9702ec00SEddy Petrișor /* 34*9702ec00SEddy Petrișor * MC_CGM_ACn_DCm_PREDIV_MASK is on 5 bits because practical test has shown 35*9702ec00SEddy Petrișor * that the 5th bit is always ignored during writes if the current 36*9702ec00SEddy Petrișor * MC_CGM_ACn_DCm_PREDIV field has only 4 bits 37*9702ec00SEddy Petrișor * 38*9702ec00SEddy Petrișor * The manual states only selectors 1, 5 and 15 have DC0_PREDIV on 5 bits 39*9702ec00SEddy Petrișor * 40*9702ec00SEddy Petrișor * This should be changed if any problems occur. 41*9702ec00SEddy Petrișor */ 42*9702ec00SEddy Petrișor #define MC_CGM_ACn_DCm_PREDIV_MASK (0x001F0000) 43*9702ec00SEddy Petrișor #define MC_CGM_ACn_DCm_PREDIV_OFFSET (16) 44*9702ec00SEddy Petrișor #define MC_CGM_ACn_DCm_DE (1 << 31) 45*9702ec00SEddy Petrișor 46*9702ec00SEddy Petrișor /* 47*9702ec00SEddy Petrișor * MC_CGM_ACn_SC/MC_CGM_ACn_SS 48*9702ec00SEddy Petrișor */ 49*9702ec00SEddy Petrișor #define CGM_ACn_SC(cgm_addr,ac) ((cgm_addr + 0x00000800) + ((ac) * 0x20)) 50*9702ec00SEddy Petrișor #define CGM_ACn_SS(cgm_addr,ac) ((cgm_addr + 0x00000804) + ((ac) * 0x20)) 51*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_MASK (0x07000000) 52*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_SET(source) (MC_CGM_ACn_SEL_MASK & (((source) & 0x7) << MC_CGM_ACn_SEL_OFFSET)) 53*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_OFFSET (24) 54*9702ec00SEddy Petrișor 55*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_FIRC (0x0) 56*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_XOSC (0x1) 57*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_ARMPLL (0x2) 58*9702ec00SEddy Petrișor /* 59*9702ec00SEddy Petrișor * According to the manual some PLL can be divided by X (X={1,3,5}): 60*9702ec00SEddy Petrișor * PERPLLDIVX, VIDEOPLLDIVX. 61*9702ec00SEddy Petrișor */ 62*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_PERPLLDIVX (0x3) 63*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_ENETPLL (0x4) 64*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_DDRPLL (0x5) 65*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_EXTSRCPAD (0x7) 66*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_SYSCLK (0x8) 67*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_VIDEOPLLDIVX (0x9) 68*9702ec00SEddy Petrișor #define MC_CGM_ACn_SEL_PERCLK (0xA) 69*9702ec00SEddy Petrișor 70*9702ec00SEddy Petrișor /* PLLDIG PLL Divider Register (PLLDIG_PLLDV) */ 71*9702ec00SEddy Petrișor #define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80)) 72*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_MFD(div) (PLLDIG_PLLDV_MFD_MASK & (div)) 73*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_MFD_MASK (0x000000FF) 74*9702ec00SEddy Petrișor 75*9702ec00SEddy Petrișor /* 76*9702ec00SEddy Petrișor * PLLDIG_PLLDV_RFDPHIB has a different format for /32 according to 77*9702ec00SEddy Petrișor * the reference manual. This other value respect the formula 2^[RFDPHIBY+1] 78*9702ec00SEddy Petrișor */ 79*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI_SET(val) (PLLDIG_PLLDV_RFDPHI_MASK & (((val) & PLLDIG_PLLDV_RFDPHI_MAXVALUE) << PLLDIG_PLLDV_RFDPHI_OFFSET)) 80*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI_MASK (0x003F0000) 81*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI_MAXVALUE (0x3F) 82*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI_OFFSET (16) 83*9702ec00SEddy Petrișor 84*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI1_SET(val) (PLLDIG_PLLDV_RFDPHI1_MASK & (((val) & PLLDIG_PLLDV_RFDPHI1_MAXVALUE) << PLLDIG_PLLDV_RFDPHI1_OFFSET)) 85*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI1_MASK (0x7E000000) 86*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI1_MAXVALUE (0x3F) 87*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_RFDPHI1_OFFSET (25) 88*9702ec00SEddy Petrișor 89*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_PREDIV_SET(val) (PLLDIG_PLLDV_PREDIV_MASK & (((val) & PLLDIG_PLLDV_PREDIV_MAXVALUE) << PLLDIG_PLLDV_PREDIV_OFFSET)) 90*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_PREDIV_MASK (0x00007000) 91*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_PREDIV_MAXVALUE (0x7) 92*9702ec00SEddy Petrișor #define PLLDIG_PLLDV_PREDIV_OFFSET (12) 93*9702ec00SEddy Petrișor 94*9702ec00SEddy Petrișor /* PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD) */ 95*9702ec00SEddy Petrișor #define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80)) 96*9702ec00SEddy Petrișor #define PLLDIG_PLLFD_MFN_SET(val) (PLLDIG_PLLFD_MFN_MASK & (val)) 97*9702ec00SEddy Petrișor #define PLLDIG_PLLFD_MFN_MASK (0x00007FFF) 98*9702ec00SEddy Petrișor #define PLLDIG_PLLFD_SMDEN (1 << 30) 99*9702ec00SEddy Petrișor 100*9702ec00SEddy Petrișor /* PLL Calibration Register 1 (PLLDIG_PLLCAL1) */ 101*9702ec00SEddy Petrișor #define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80)) 102*9702ec00SEddy Petrișor #define PLLDIG_PLLCAL1_NDAC1_SET(val) (PLLDIG_PLLCAL1_NDAC1_MASK & ((val) << PLLDIG_PLLCAL1_NDAC1_OFFSET)) 103*9702ec00SEddy Petrișor #define PLLDIG_PLLCAL1_NDAC1_OFFSET (24) 104*9702ec00SEddy Petrișor #define PLLDIG_PLLCAL1_NDAC1_MASK (0x7F000000) 105*9702ec00SEddy Petrișor 106*9702ec00SEddy Petrișor /* Digital Frequency Synthesizer (DFS) */ 107*9702ec00SEddy Petrișor /* According to the manual there are 3 DFS modules only for ARM_PLL, DDR_PLL, ENET_PLL */ 108*9702ec00SEddy Petrișor #define DFS0_BASE_ADDR (MC_CGM0_BASE_ADDR + 0x00000040) 109*9702ec00SEddy Petrișor 110*9702ec00SEddy Petrișor /* DFS DLL Program Register 1 */ 111*9702ec00SEddy Petrișor #define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80)) 112*9702ec00SEddy Petrișor 113*9702ec00SEddy Petrișor #define DFS_DLLPRG1_V2IGC_SET(val) (DFS_DLLPRG1_V2IGC_MASK & ((val) << DFS_DLLPRG1_V2IGC_OFFSET)) 114*9702ec00SEddy Petrișor #define DFS_DLLPRG1_V2IGC_OFFSET (0) 115*9702ec00SEddy Petrișor #define DFS_DLLPRG1_V2IGC_MASK (0x00000007) 116*9702ec00SEddy Petrișor 117*9702ec00SEddy Petrișor #define DFS_DLLPRG1_LCKWT_SET(val) (DFS_DLLPRG1_LCKWT_MASK & ((val) << DFS_DLLPRG1_LCKWT_OFFSET)) 118*9702ec00SEddy Petrișor #define DFS_DLLPRG1_LCKWT_OFFSET (4) 119*9702ec00SEddy Petrișor #define DFS_DLLPRG1_LCKWT_MASK (0x00000030) 120*9702ec00SEddy Petrișor 121*9702ec00SEddy Petrișor #define DFS_DLLPRG1_DACIN_SET(val) (DFS_DLLPRG1_DACIN_MASK & ((val) << DFS_DLLPRG1_DACIN_OFFSET)) 122*9702ec00SEddy Petrișor #define DFS_DLLPRG1_DACIN_OFFSET (6) 123*9702ec00SEddy Petrișor #define DFS_DLLPRG1_DACIN_MASK (0x000001C0) 124*9702ec00SEddy Petrișor 125*9702ec00SEddy Petrișor #define DFS_DLLPRG1_CALBYPEN_SET(val) (DFS_DLLPRG1_CALBYPEN_MASK & ((val) << DFS_DLLPRG1_CALBYPEN_OFFSET)) 126*9702ec00SEddy Petrișor #define DFS_DLLPRG1_CALBYPEN_OFFSET (9) 127*9702ec00SEddy Petrișor #define DFS_DLLPRG1_CALBYPEN_MASK (0x00000200) 128*9702ec00SEddy Petrișor 129*9702ec00SEddy Petrișor #define DFS_DLLPRG1_VSETTLCTRL_SET(val) (DFS_DLLPRG1_VSETTLCTRL_MASK & ((val) << DFS_DLLPRG1_VSETTLCTRL_OFFSET)) 130*9702ec00SEddy Petrișor #define DFS_DLLPRG1_VSETTLCTRL_OFFSET (10) 131*9702ec00SEddy Petrișor #define DFS_DLLPRG1_VSETTLCTRL_MASK (0x00000C00) 132*9702ec00SEddy Petrișor 133*9702ec00SEddy Petrișor #define DFS_DLLPRG1_CPICTRL_SET(val) (DFS_DLLPRG1_CPICTRL_MASK & ((val) << DFS_DLLPRG1_CPICTRL_OFFSET)) 134*9702ec00SEddy Petrișor #define DFS_DLLPRG1_CPICTRL_OFFSET (12) 135*9702ec00SEddy Petrișor #define DFS_DLLPRG1_CPICTRL_MASK (0x00007000) 136*9702ec00SEddy Petrișor 137*9702ec00SEddy Petrișor /* DFS Control Register (DFS_CTRL) */ 138*9702ec00SEddy Petrișor #define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80)) 139*9702ec00SEddy Petrișor #define DFS_CTRL_DLL_LOLIE (1 << 0) 140*9702ec00SEddy Petrișor #define DFS_CTRL_DLL_RESET (1 << 1) 141*9702ec00SEddy Petrișor 142*9702ec00SEddy Petrișor /* DFS Port Status Register (DFS_PORTSR) */ 143*9702ec00SEddy Petrișor #define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80)) 144*9702ec00SEddy Petrișor /* DFS Port Reset Register (DFS_PORTRESET) */ 145*9702ec00SEddy Petrișor #define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80)) 146*9702ec00SEddy Petrișor #define DFS_PORTRESET_PORTRESET_SET(val) (DFS_PORTRESET_PORTRESET_MASK | (((val) & DFS_PORTRESET_PORTRESET_MAXVAL) << DFS_PORTRESET_PORTRESET_OFFSET)) 147*9702ec00SEddy Petrișor #define DFS_PORTRESET_PORTRESET_MAXVAL (0xF) 148*9702ec00SEddy Petrișor #define DFS_PORTRESET_PORTRESET_MASK (0x0000000F) 149*9702ec00SEddy Petrișor #define DFS_PORTRESET_PORTRESET_OFFSET (0) 150*9702ec00SEddy Petrișor 151*9702ec00SEddy Petrișor /* DFS Divide Register Portn (DFS_DVPORTn) */ 152*9702ec00SEddy Petrișor #define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4))) 153*9702ec00SEddy Petrișor 154*9702ec00SEddy Petrișor /* 155*9702ec00SEddy Petrișor * The mathematical formula for fdfs_clockout is the following: 156*9702ec00SEddy Petrișor * fdfs_clckout = fdfs_clkin / ( DFS_DVPORTn[MFI] + (DFS_DVPORTn[MFN]/256) ) 157*9702ec00SEddy Petrișor */ 158*9702ec00SEddy Petrișor #define DFS_DVPORTn_MFI_SET(val) (DFS_DVPORTn_MFI_MASK & (((val) & DFS_DVPORTn_MFI_MAXVAL) << DFS_DVPORTn_MFI_OFFSET) ) 159*9702ec00SEddy Petrișor #define DFS_DVPORTn_MFN_SET(val) (DFS_DVPORTn_MFN_MASK & (((val) & DFS_DVPORTn_MFN_MAXVAL) << DFS_DVPORTn_MFN_OFFSET) ) 160*9702ec00SEddy Petrișor #define DFS_DVPORTn_MFI_MASK (0x0000FF00) 161*9702ec00SEddy Petrișor #define DFS_DVPORTn_MFN_MASK (0x000000FF) 162*9702ec00SEddy Petrișor #define DFS_DVPORTn_MFI_MAXVAL (0xFF) 163*9702ec00SEddy Petrișor #define DFS_DVPORTn_MFN_MAXVAL (0xFF) 164*9702ec00SEddy Petrișor #define DFS_DVPORTn_MFI_OFFSET (8) 165*9702ec00SEddy Petrișor #define DFS_DVPORTn_MFN_OFFSET (0) 166*9702ec00SEddy Petrișor #define DFS_MAXNUMBER (4) 167*9702ec00SEddy Petrișor 168*9702ec00SEddy Petrișor #define DFS_PARAMS_Nr (3) 169*9702ec00SEddy Petrișor 170*9702ec00SEddy Petrișor /* Frequencies are in Hz */ 171*9702ec00SEddy Petrișor #define FIRC_CLK_FREQ (48000000) 172*9702ec00SEddy Petrișor #define XOSC_CLK_FREQ (40000000) 173*9702ec00SEddy Petrișor 174*9702ec00SEddy Petrișor #define PLL_MIN_FREQ (650000000) 175*9702ec00SEddy Petrișor #define PLL_MAX_FREQ (1300000000) 176*9702ec00SEddy Petrișor 177*9702ec00SEddy Petrișor #define ARM_PLL_PHI0_FREQ (1000000000) 178*9702ec00SEddy Petrișor #define ARM_PLL_PHI1_FREQ (1000000000) 179*9702ec00SEddy Petrișor /* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */ 180*9702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS1_EN (1) 181*9702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS1_MFI (3) 182*9702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS1_MFN (194) 183*9702ec00SEddy Petrișor /* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */ 184*9702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS2_EN (1) 185*9702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS2_MFI (1) 186*9702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS2_MFN (170) 187*9702ec00SEddy Petrișor /* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */ 188*9702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS3_EN (1) 189*9702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS3_MFI (1) 190*9702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS3_MFN (170) 191*9702ec00SEddy Petrișor #define ARM_PLL_PHI1_DFS_Nr (3) 192*9702ec00SEddy Petrișor #define ARM_PLL_PLLDV_PREDIV (2) 193*9702ec00SEddy Petrișor #define ARM_PLL_PLLDV_MFD (50) 194*9702ec00SEddy Petrișor #define ARM_PLL_PLLDV_MFN (0) 195*9702ec00SEddy Petrișor 196*9702ec00SEddy Petrișor #define PERIPH_PLL_PHI0_FREQ (400000000) 197*9702ec00SEddy Petrișor #define PERIPH_PLL_PHI1_FREQ (100000000) 198*9702ec00SEddy Petrișor #define PERIPH_PLL_PHI1_DFS_Nr (0) 199*9702ec00SEddy Petrișor #define PERIPH_PLL_PLLDV_PREDIV (1) 200*9702ec00SEddy Petrișor #define PERIPH_PLL_PLLDV_MFD (30) 201*9702ec00SEddy Petrișor #define PERIPH_PLL_PLLDV_MFN (0) 202*9702ec00SEddy Petrișor 203*9702ec00SEddy Petrișor #define ENET_PLL_PHI0_FREQ (500000000) 204*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_FREQ (1000000000) 205*9702ec00SEddy Petrișor /* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/ 206*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS1_EN (1) 207*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS1_MFI (2) 208*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS1_MFN (219) 209*9702ec00SEddy Petrișor /* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/ 210*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS2_EN (1) 211*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS2_MFI (2) 212*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS2_MFN (219) 213*9702ec00SEddy Petrișor /* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/ 214*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS3_EN (1) 215*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS3_MFI (3) 216*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS3_MFN (32) 217*9702ec00SEddy Petrișor /* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/ 218*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS4_EN (1) 219*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS4_MFI (2) 220*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS4_MFN (0) 221*9702ec00SEddy Petrișor #define ENET_PLL_PHI1_DFS_Nr (4) 222*9702ec00SEddy Petrișor #define ENET_PLL_PLLDV_PREDIV (2) 223*9702ec00SEddy Petrișor #define ENET_PLL_PLLDV_MFD (50) 224*9702ec00SEddy Petrișor #define ENET_PLL_PLLDV_MFN (0) 225*9702ec00SEddy Petrișor 226*9702ec00SEddy Petrișor #define DDR_PLL_PHI0_FREQ (533000000) 227*9702ec00SEddy Petrișor #define DDR_PLL_PHI1_FREQ (1066000000) 228*9702ec00SEddy Petrișor /* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */ 229*9702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS1_EN (1) 230*9702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS1_MFI (2) 231*9702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS1_MFN (33) 232*9702ec00SEddy Petrișor /* DDR_PLL_PHI1_DFS2_REQ - 500 Mhz */ 233*9702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS2_EN (1) 234*9702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS2_MFI (2) 235*9702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS2_MFN (33) 236*9702ec00SEddy Petrișor /* DDR_PLL_PHI1_DFS3_FREQ - 350 Mhz */ 237*9702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS3_EN (1) 238*9702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS3_MFI (3) 239*9702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS3_MFN (11) 240*9702ec00SEddy Petrișor #define DDR_PLL_PHI1_DFS_Nr (3) 241*9702ec00SEddy Petrișor #define DDR_PLL_PLLDV_PREDIV (2) 242*9702ec00SEddy Petrișor #define DDR_PLL_PLLDV_MFD (53) 243*9702ec00SEddy Petrișor #define DDR_PLL_PLLDV_MFN (6144) 244*9702ec00SEddy Petrișor 245*9702ec00SEddy Petrișor #define VIDEO_PLL_PHI0_FREQ (600000000) 246*9702ec00SEddy Petrișor #define VIDEO_PLL_PHI1_FREQ (0) 247*9702ec00SEddy Petrișor #define VIDEO_PLL_PHI1_DFS_Nr (0) 248*9702ec00SEddy Petrișor #define VIDEO_PLL_PLLDV_PREDIV (1) 249*9702ec00SEddy Petrișor #define VIDEO_PLL_PLLDV_MFD (30) 250*9702ec00SEddy Petrișor #define VIDEO_PLL_PLLDV_MFN (0) 251*9702ec00SEddy Petrișor 252*9702ec00SEddy Petrișor #endif 253*9702ec00SEddy Petrișor 254*9702ec00SEddy Petrișor #endif /*__ARCH_ARM_MACH_S32V234_MCCGM_REGS_H__ */ 255