1 /* 2 * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ARCH_ARM_MACH_S32V234_LPDDR2_H__ 8 #define __ARCH_ARM_MACH_S32V234_LPDDR2_H__ 9 10 /* definitions for LPDDR2 PAD values */ 11 #define LPDDR2_CLK0_PAD \ 12 (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ 13 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_CRPOINT_TRIM_1 | \ 14 SIUL2_MSCR_DCYCLE_TRIM_NONE) 15 #define LPDDR2_CKEn_PAD \ 16 (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ 17 SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm) 18 #define LPDDR2_CS_Bn_PAD \ 19 (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ 20 SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm) 21 #define LPDDR2_DMn_PAD \ 22 (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm |\ 23 SIUL2_MSCR_PUS_100K_UP | SIUL2_MSCR_DSE_48ohm) 24 #define LPDDR2_DQSn_PAD \ 25 (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \ 26 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_PUE_EN | SIUL2_MSCR_PUS_100K_DOWN | \ 27 SIUL2_MSCR_PKE_EN | SIUL2_MSCR_CRPOINT_TRIM_1 | SIUL2_MSCR_DCYCLE_TRIM_NONE) 28 #define LPDDR2_An_PAD \ 29 (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \ 30 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \ 31 SIUL2_MSCR_PUS_100K_UP) 32 #define LPDDR2_Dn_PAD \ 33 (SIUL2_MSCR_DDR_SEL_LPDDR2 | SIUL2_MSCR_DDR_INPUT_DIFF_DDR | SIUL2_MSCR_DDR_ODT_120ohm | \ 34 SIUL2_MSCR_DSE_48ohm | SIUL2_MSCR_DDR_DO_TRIM_50PS | SIUL2_MSCR_DCYCLE_TRIM_LEFT | \ 35 SIUL2_MSCR_PUS_100K_UP) 36 37 #define _MDCTL 0x03010000 38 39 #define MMDC_MDSCR_CFG_VALUE 0x00008000 /* Set MDSCR[CON_REQ] (configuration request) */ 40 #define MMDC_MDCFG0_VALUE 0x464F61A5 /* tRFCab=70 (=130ns),tXSR=80 (=tRFCab+10ns),tXP=4 (=7.5ns),tXPDLL=n/a,tFAW=27 (50 ns),tCL(RL)=8 */ 41 #define MMDC_MDCFG1_VALUE 0x00180E63 /* tRCD=n/a,tRPpb=n/a,tRC=n/a ,tRAS=25 (=47ns),tRPA=n/a,tWR=8 (=15.0ns),tMRD=3,tWL=4 */ 42 #define MMDC_MDCFG2_VALUE 0x000000DD /* tDLLK=n/a,tRTP=4 (=7.5ns),tWTR=4 (=7.5ns),tRRD=6 (=10ns) */ 43 #define MMDC_MDCFG3LP_VALUE 0x001F099B /* RC_LP=tRAS+tRPab=32 (>60ns), tRCD_LP=10 (18ns) , tRPpb_LP=10 (18ns), tRPab_LP=12 (21ns) */ 44 #define MMDC_MDOTC_VALUE 0x00000000 /* tAOFPD=n/a,tAONPD=n/a,tANPD=n/a,tAXPD=n/a,tODTLon=n/a,tODT_idle_off=n/a */ 45 #define MMDC_MDMISC_VALUE 0x00001688 /* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */ 46 #define MMDC_MDOR_VALUE 0x00000010 /* tXPR=n/a , SDE_to_RST=n/a, RST_to_CKE=14 */ 47 #define MMDC_MPMUR0_VALUE 0x00000800 /* Force delay line initialisation */ 48 #define MMDC_MDSCR_RST_VALUE 0x003F8030 /* Reset command CS0 */ 49 #define MMDC_MPZQLP2CTL_VALUE 0x1B5F0109 /* ZQ_LP2_HW_ZQCS=0x1B (90ns spec), ZQ_LP2_HW_ZQCL=0x5F (160ns spec), ZQ_LP2_HW_ZQINIT=0x109 (1us spec) */ 50 #define MMDC_MPZQHWCTRL_VALUE 0xA0010003 /* ZQ_EARLY_COMPARATOR_EN_TIMER=0x14, TZQ_CS=n/a, TZQ_OPER=n/a, TZQ_INIT=n/a, ZQ_HW_FOR=1, ZQ_HW_PER=0, ZQ_MODE=3 */ 51 #define MMDC_MDSCR_MR1_VALUE 0xC2018030 /* Configure MR1: BL 4, burst type interleaved, wrap control no wrap, tWR cycles 8 */ 52 #define MMDC_MDSCR_MR2_VALUE 0x06028030 /* Configure MR2: RL=8, WL=4 */ 53 #define MMDC_MDSCR_MR3_VALUE 0x01038030 /* Configure MR3: DS=34R */ 54 #define MMDC_MDSCR_MR10_VALUE 0xFF0A8030 /* Configure MR10: Calibration at init */ 55 #define MMDC_MDASP_MODULE0_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0x90000000) */ 56 #define MMDC_MPRDDLCTL_MODULE0_VALUE 0x4D4B4F4B /* Read delay line offsets */ 57 #define MMDC_MPWRDLCTL_MODULE0_VALUE 0x38383737 /* Write delay line offsets */ 58 #define MMDC_MPDGCTRL0_MODULE0_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */ 59 #define MMDC_MPDGCTRL1_MODULE0_VALUE 0x00000000 /* Read DQS gating control 1 */ 60 #define MMDC_MDASP_MODULE1_VALUE 0x0000007F /* 2Gb, 256 MB memory so CS0 is 256 MB (0xD0000000) */ 61 #define MMDC_MPRDDLCTL_MODULE1_VALUE 0x4D4B4F4B /* Read delay line offsets */ 62 #define MMDC_MPWRDLCTL_MODULE1_VALUE 0x38383737 /* Write delay line offsets */ 63 #define MMDC_MPDGCTRL0_MODULE1_VALUE 0x20000000 /* Read DQS gating control 0 (disabled) */ 64 #define MMDC_MPDGCTRL1_MODULE1_VALUE 0x00000000 /* Read DQS gating control 1 */ 65 #define MMDC_MDRWD_VALUE 0x0F9F26D2 /* Read/write command delay - default used */ 66 #define MMDC_MDPDC_VALUE 0x00020024 /* Power down control */ 67 #define MMDC_MDREF_VALUE 0x30B01800 /* Refresh control */ 68 #define MMDC_MPODTCTRL_VALUE 0x00000000 /* No ODT */ 69 #define MMDC_MDSCR_DEASSERT_VALUE 0x00000000 /* Deassert the configuration request */ 70 71 /* set I/O pads for DDR */ 72 void lpddr2_config_iomux(uint8_t module); 73 void config_mmdc(uint8_t module); 74 75 #endif 76