1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __ARCH_ARM_MACH_S32V234_DDR_H__ 7 #define __ARCH_ARM_MACH_S32V234_DDR_H__ 8 9 #define DDR0 0 10 #define DDR1 1 11 12 /* DDR offset in MSCR register */ 13 #define _DDR0_RESET 168 14 #define _DDR0_CLK0 169 15 #define _DDR0_CAS 170 16 #define _DDR0_RAS 171 17 #define _DDR0_WE_B 172 18 #define _DDR0_CKE0 173 19 #define _DDR0_CKE1 174 20 #define _DDR0_CS_B0 175 21 #define _DDR0_CS_B1 176 22 #define _DDR0_BA0 177 23 #define _DDR0_BA1 178 24 #define _DDR0_BA2 179 25 #define _DDR0_A0 180 26 #define _DDR0_A1 181 27 #define _DDR0_A2 182 28 #define _DDR0_A3 183 29 #define _DDR0_A4 184 30 #define _DDR0_A5 185 31 #define _DDR0_A6 186 32 #define _DDR0_A7 187 33 #define _DDR0_A8 188 34 #define _DDR0_A9 189 35 #define _DDR0_A10 190 36 #define _DDR0_A11 191 37 #define _DDR0_A12 192 38 #define _DDR0_A13 193 39 #define _DDR0_A14 194 40 #define _DDR0_A15 195 41 #define _DDR0_DM0 196 42 #define _DDR0_DM1 197 43 #define _DDR0_DM2 198 44 #define _DDR0_DM3 199 45 #define _DDR0_DQS0 200 46 #define _DDR0_DQS1 201 47 #define _DDR0_DQS2 202 48 #define _DDR0_DQS3 203 49 #define _DDR0_D0 204 50 #define _DDR0_D1 205 51 #define _DDR0_D2 206 52 #define _DDR0_D3 207 53 #define _DDR0_D4 208 54 #define _DDR0_D5 209 55 #define _DDR0_D6 210 56 #define _DDR0_D7 211 57 #define _DDR0_D8 212 58 #define _DDR0_D9 213 59 #define _DDR0_D10 214 60 #define _DDR0_D11 215 61 #define _DDR0_D12 216 62 #define _DDR0_D13 217 63 #define _DDR0_D14 218 64 #define _DDR0_D15 219 65 #define _DDR0_D16 220 66 #define _DDR0_D17 221 67 #define _DDR0_D18 222 68 #define _DDR0_D19 223 69 #define _DDR0_D20 224 70 #define _DDR0_D21 225 71 #define _DDR0_D22 226 72 #define _DDR0_D23 227 73 #define _DDR0_D24 228 74 #define _DDR0_D25 229 75 #define _DDR0_D26 230 76 #define _DDR0_D27 231 77 #define _DDR0_D28 232 78 #define _DDR0_D29 233 79 #define _DDR0_D30 234 80 #define _DDR0_D31 235 81 #define _DDR0_ODT0 236 82 #define _DDR0_ODT1 237 83 #define _DDR0_ZQ 238 84 #define _DDR1_RESET 239 85 #define _DDR1_CLK0 240 86 #define _DDR1_CAS 241 87 #define _DDR1_RAS 242 88 #define _DDR1_WE_B 243 89 #define _DDR1_CKE0 244 90 #define _DDR1_CKE1 245 91 #define _DDR1_CS_B0 246 92 #define _DDR1_CS_B1 247 93 #define _DDR1_BA0 248 94 #define _DDR1_BA1 249 95 #define _DDR1_BA2 250 96 #define _DDR1_A0 251 97 #define _DDR1_A1 252 98 #define _DDR1_A2 253 99 #define _DDR1_A3 254 100 #define _DDR1_A4 255 101 #define _DDR1_A5 256 102 #define _DDR1_A6 257 103 #define _DDR1_A7 258 104 #define _DDR1_A8 259 105 #define _DDR1_A9 260 106 #define _DDR1_A10 261 107 #define _DDR1_A11 262 108 #define _DDR1_A12 263 109 #define _DDR1_A13 264 110 #define _DDR1_A14 265 111 #define _DDR1_A15 266 112 #define _DDR1_DM0 267 113 #define _DDR1_DM1 268 114 #define _DDR1_DM2 269 115 #define _DDR1_DM3 270 116 #define _DDR1_DQS0 271 117 #define _DDR1_DQS1 272 118 #define _DDR1_DQS2 273 119 #define _DDR1_DQS3 274 120 #define _DDR1_D0 275 121 #define _DDR1_D1 276 122 #define _DDR1_D2 277 123 #define _DDR1_D3 278 124 #define _DDR1_D4 279 125 #define _DDR1_D5 280 126 #define _DDR1_D6 281 127 #define _DDR1_D7 282 128 #define _DDR1_D8 283 129 #define _DDR1_D9 284 130 #define _DDR1_D10 285 131 #define _DDR1_D11 286 132 #define _DDR1_D12 287 133 #define _DDR1_D13 288 134 #define _DDR1_D14 289 135 #define _DDR1_D15 290 136 #define _DDR1_D16 291 137 #define _DDR1_D17 292 138 #define _DDR1_D18 293 139 #define _DDR1_D19 294 140 #define _DDR1_D20 295 141 #define _DDR1_D21 296 142 #define _DDR1_D22 297 143 #define _DDR1_D23 298 144 #define _DDR1_D24 299 145 #define _DDR1_D25 300 146 #define _DDR1_D26 301 147 #define _DDR1_D27 302 148 #define _DDR1_D28 303 149 #define _DDR1_D29 304 150 #define _DDR1_D30 305 151 #define _DDR1_D31 306 152 #define _DDR1_ODT0 307 153 #define _DDR1_ODT1 308 154 #define _DDR1_ZQ 309 155 156 #endif 157