1 /* 2 * (C) Copyright 2015-2016, Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __ARCH_ARM_MACH_S32V234_DDR_H__ 8 #define __ARCH_ARM_MACH_S32V234_DDR_H__ 9 10 #define DDR0 0 11 #define DDR1 1 12 13 /* DDR offset in MSCR register */ 14 #define _DDR0_RESET 168 15 #define _DDR0_CLK0 169 16 #define _DDR0_CAS 170 17 #define _DDR0_RAS 171 18 #define _DDR0_WE_B 172 19 #define _DDR0_CKE0 173 20 #define _DDR0_CKE1 174 21 #define _DDR0_CS_B0 175 22 #define _DDR0_CS_B1 176 23 #define _DDR0_BA0 177 24 #define _DDR0_BA1 178 25 #define _DDR0_BA2 179 26 #define _DDR0_A0 180 27 #define _DDR0_A1 181 28 #define _DDR0_A2 182 29 #define _DDR0_A3 183 30 #define _DDR0_A4 184 31 #define _DDR0_A5 185 32 #define _DDR0_A6 186 33 #define _DDR0_A7 187 34 #define _DDR0_A8 188 35 #define _DDR0_A9 189 36 #define _DDR0_A10 190 37 #define _DDR0_A11 191 38 #define _DDR0_A12 192 39 #define _DDR0_A13 193 40 #define _DDR0_A14 194 41 #define _DDR0_A15 195 42 #define _DDR0_DM0 196 43 #define _DDR0_DM1 197 44 #define _DDR0_DM2 198 45 #define _DDR0_DM3 199 46 #define _DDR0_DQS0 200 47 #define _DDR0_DQS1 201 48 #define _DDR0_DQS2 202 49 #define _DDR0_DQS3 203 50 #define _DDR0_D0 204 51 #define _DDR0_D1 205 52 #define _DDR0_D2 206 53 #define _DDR0_D3 207 54 #define _DDR0_D4 208 55 #define _DDR0_D5 209 56 #define _DDR0_D6 210 57 #define _DDR0_D7 211 58 #define _DDR0_D8 212 59 #define _DDR0_D9 213 60 #define _DDR0_D10 214 61 #define _DDR0_D11 215 62 #define _DDR0_D12 216 63 #define _DDR0_D13 217 64 #define _DDR0_D14 218 65 #define _DDR0_D15 219 66 #define _DDR0_D16 220 67 #define _DDR0_D17 221 68 #define _DDR0_D18 222 69 #define _DDR0_D19 223 70 #define _DDR0_D20 224 71 #define _DDR0_D21 225 72 #define _DDR0_D22 226 73 #define _DDR0_D23 227 74 #define _DDR0_D24 228 75 #define _DDR0_D25 229 76 #define _DDR0_D26 230 77 #define _DDR0_D27 231 78 #define _DDR0_D28 232 79 #define _DDR0_D29 233 80 #define _DDR0_D30 234 81 #define _DDR0_D31 235 82 #define _DDR0_ODT0 236 83 #define _DDR0_ODT1 237 84 #define _DDR0_ZQ 238 85 #define _DDR1_RESET 239 86 #define _DDR1_CLK0 240 87 #define _DDR1_CAS 241 88 #define _DDR1_RAS 242 89 #define _DDR1_WE_B 243 90 #define _DDR1_CKE0 244 91 #define _DDR1_CKE1 245 92 #define _DDR1_CS_B0 246 93 #define _DDR1_CS_B1 247 94 #define _DDR1_BA0 248 95 #define _DDR1_BA1 249 96 #define _DDR1_BA2 250 97 #define _DDR1_A0 251 98 #define _DDR1_A1 252 99 #define _DDR1_A2 253 100 #define _DDR1_A3 254 101 #define _DDR1_A4 255 102 #define _DDR1_A5 256 103 #define _DDR1_A6 257 104 #define _DDR1_A7 258 105 #define _DDR1_A8 259 106 #define _DDR1_A9 260 107 #define _DDR1_A10 261 108 #define _DDR1_A11 262 109 #define _DDR1_A12 263 110 #define _DDR1_A13 264 111 #define _DDR1_A14 265 112 #define _DDR1_A15 266 113 #define _DDR1_DM0 267 114 #define _DDR1_DM1 268 115 #define _DDR1_DM2 269 116 #define _DDR1_DM3 270 117 #define _DDR1_DQS0 271 118 #define _DDR1_DQS1 272 119 #define _DDR1_DQS2 273 120 #define _DDR1_DQS3 274 121 #define _DDR1_D0 275 122 #define _DDR1_D1 276 123 #define _DDR1_D2 277 124 #define _DDR1_D3 278 125 #define _DDR1_D4 279 126 #define _DDR1_D5 280 127 #define _DDR1_D6 281 128 #define _DDR1_D7 282 129 #define _DDR1_D8 283 130 #define _DDR1_D9 284 131 #define _DDR1_D10 285 132 #define _DDR1_D11 286 133 #define _DDR1_D12 287 134 #define _DDR1_D13 288 135 #define _DDR1_D14 289 136 #define _DDR1_D15 290 137 #define _DDR1_D16 291 138 #define _DDR1_D17 292 139 #define _DDR1_D18 293 140 #define _DDR1_D19 294 141 #define _DDR1_D20 295 142 #define _DDR1_D21 296 143 #define _DDR1_D22 297 144 #define _DDR1_D23 298 145 #define _DDR1_D24 299 146 #define _DDR1_D25 300 147 #define _DDR1_D26 301 148 #define _DDR1_D27 302 149 #define _DDR1_D28 303 150 #define _DDR1_D29 304 151 #define _DDR1_D30 305 152 #define _DDR1_D31 306 153 #define _DDR1_ODT0 307 154 #define _DDR1_ODT1 308 155 #define _DDR1_ZQ 309 156 157 #endif 158