1 /*
2  * (C) Copyright 2016 Rockchip Electronics Co.,Ltd
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef _ASM_ARCH_SYS_PROTO_H
8 #define _ASM_ARCH_SYS_PROTO_H
9 
10 #ifdef CONFIG_ROCKCHIP_RK3288
11 #include <asm/armv7.h>
12 
13 static void configure_l2ctlr(void)
14 {
15 	uint32_t l2ctlr;
16 
17 	l2ctlr = read_l2ctlr();
18 	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
19 
20 	/*
21 	* Data RAM write latency: 2 cycles
22 	* Data RAM read latency: 2 cycles
23 	* Data RAM setup latency: 1 cycle
24 	* Tag RAM write latency: 1 cycle
25 	* Tag RAM read latency: 1 cycle
26 	* Tag RAM setup latency: 1 cycle
27 	*/
28 	l2ctlr |= (1 << 3 | 1 << 0);
29 	write_l2ctlr(l2ctlr);
30 }
31 #endif /* CONFIG_ROCKCHIP_RK3288 */
32 
33 #endif /* _ASM_ARCH_SYS_PROTO_H */
34