1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2016 Rockchip Electronics Co.,Ltd
4  */
5 
6 #ifndef _ASM_ARCH_SYS_PROTO_H
7 #define _ASM_ARCH_SYS_PROTO_H
8 
9 #ifdef CONFIG_ROCKCHIP_RK3288
10 #include <asm/armv7.h>
11 
12 static void configure_l2ctlr(void)
13 {
14 	uint32_t l2ctlr;
15 
16 	l2ctlr = read_l2ctlr();
17 	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
18 
19 	/*
20 	* Data RAM write latency: 2 cycles
21 	* Data RAM read latency: 2 cycles
22 	* Data RAM setup latency: 1 cycle
23 	* Tag RAM write latency: 1 cycle
24 	* Tag RAM read latency: 1 cycle
25 	* Tag RAM setup latency: 1 cycle
26 	*/
27 	l2ctlr |= (1 << 3 | 1 << 0);
28 	write_l2ctlr(l2ctlr);
29 }
30 #endif /* CONFIG_ROCKCHIP_RK3288 */
31 
32 #endif /* _ASM_ARCH_SYS_PROTO_H */
33