1 /* 2 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * author: Eric Gao <eric.gao@rock-chips.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef ROCKCHIP_MIPI_DSI_H 9 #define ROCKCHIP_MIPI_DSI_H 10 11 /* 12 * All these mipi controller register declaration provide reg address offset, 13 * bits width, bit offset for a specified register bits. With these message, we 14 * can set or clear every bits individually for a 32bit widthregister. We use 15 * DSI_HOST_BITS macro definition to combinat these message using the following 16 * format: val(32bit) = addr(16bit) | width(8bit) | offest(8bit) 17 * For example: 18 * #define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0) 19 * means SHUTDOWNZ is a signal reg bit with bit offset qual 0,and it's reg addr 20 * offset is 0x004.The conbinat result = (0x004 << 16) | (1 << 8) | 0 21 */ 22 #define ADDR_SHIFT 16 23 #define BITS_SHIFT 8 24 #define OFFSET_SHIFT 0 25 #define DSI_HOST_BITS(addr, bits, bit_offset) \ 26 ((addr << ADDR_SHIFT) | (bits << BITS_SHIFT) | (bit_offset << OFFSET_SHIFT)) 27 28 /* DWC_DSI_VERSION_0x3133302A */ 29 #define VERSION DSI_HOST_BITS(0x000, 32, 0) 30 #define SHUTDOWNZ DSI_HOST_BITS(0x004, 1, 0) 31 #define TO_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 8) 32 #define TX_ESC_CLK_DIVISION DSI_HOST_BITS(0x008, 8, 0) 33 #define DPI_VCID DSI_HOST_BITS(0x00c, 2, 0) 34 #define EN18_LOOSELY DSI_HOST_BITS(0x010, 1, 8) 35 #define DPI_COLOR_CODING DSI_HOST_BITS(0x010, 4, 0) 36 #define COLORM_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 4) 37 #define SHUTD_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 3) 38 #define HSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 2) 39 #define VSYNC_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 1) 40 #define DATAEN_ACTIVE_LOW DSI_HOST_BITS(0x014, 1, 0) 41 #define OUTVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 16) 42 #define INVACT_LPCMD_TIME DSI_HOST_BITS(0x018, 8, 0) 43 #define CRC_RX_EN DSI_HOST_BITS(0x02c, 1, 4) 44 #define ECC_RX_EN DSI_HOST_BITS(0x02c, 1, 3) 45 #define BTA_EN DSI_HOST_BITS(0x02c, 1, 2) 46 #define EOTP_RX_EN DSI_HOST_BITS(0x02c, 1, 1) 47 #define EOTP_TX_EN DSI_HOST_BITS(0x02c, 1, 0) 48 #define GEN_VID_RX DSI_HOST_BITS(0x030, 2, 0) 49 #define CMD_VIDEO_MODE DSI_HOST_BITS(0x034, 1, 0) 50 #define VPG_ORIENTATION DSI_HOST_BITS(0x038, 1, 24) 51 #define VPG_MODE DSI_HOST_BITS(0x038, 1, 20) 52 #define VPG_EN DSI_HOST_BITS(0x038, 1, 16) 53 #define LP_CMD_EN DSI_HOST_BITS(0x038, 1, 15) 54 #define FRAME_BTA_ACK_EN DSI_HOST_BITS(0x038, 1, 14) 55 #define LP_HFP_EN DSI_HOST_BITS(0x038, 1, 13) 56 #define LP_HBP_EN DSI_HOST_BITS(0x038, 1, 12) 57 #define LP_VACT_EN DSI_HOST_BITS(0x038, 1, 11) 58 #define LP_VFP_EN DSI_HOST_BITS(0x038, 1, 10) 59 #define LP_VBP_EN DSI_HOST_BITS(0x038, 1, 9) 60 #define LP_VSA_EN DSI_HOST_BITS(0x038, 1, 8) 61 #define VID_MODE_TYPE DSI_HOST_BITS(0x038, 2, 0) 62 #define VID_PKT_SIZE DSI_HOST_BITS(0x03c, 14, 0) 63 #define NUM_CHUNKS DSI_HOST_BITS(0x040, 13, 0) 64 #define NULL_PKT_SIZE DSI_HOST_BITS(0x044, 13, 0) 65 #define VID_HSA_TIME DSI_HOST_BITS(0x048, 12, 0) 66 #define VID_HBP_TIME DSI_HOST_BITS(0x04c, 12, 0) 67 #define VID_HLINE_TIME DSI_HOST_BITS(0x050, 15, 0) 68 #define VID_VSA_LINES DSI_HOST_BITS(0x054, 10, 0) 69 #define VID_VBP_LINES DSI_HOST_BITS(0x058, 10, 0) 70 #define VID_VFP_LINES DSI_HOST_BITS(0x05c, 10, 0) 71 #define VID_ACTIVE_LINES DSI_HOST_BITS(0x060, 14, 0) 72 #define EDPI_CMD_SIZE DSI_HOST_BITS(0x064, 16, 0) 73 #define MAX_RD_PKT_SIZE DSI_HOST_BITS(0x068, 1, 24) 74 #define DCS_LW_TX DSI_HOST_BITS(0x068, 1, 19) 75 #define DCS_SR_0P_TX DSI_HOST_BITS(0x068, 1, 18) 76 #define DCS_SW_1P_TX DSI_HOST_BITS(0x068, 1, 17) 77 #define DCS_SW_0P_TX DSI_HOST_BITS(0x068, 1, 16) 78 #define GEN_LW_TX DSI_HOST_BITS(0x068, 1, 14) 79 #define GEN_SR_2P_TX DSI_HOST_BITS(0x068, 1, 13) 80 #define GEN_SR_1P_TX DSI_HOST_BITS(0x068, 1, 12) 81 #define GEN_SR_0P_TX DSI_HOST_BITS(0x068, 1, 11) 82 #define GEN_SW_2P_TX DSI_HOST_BITS(0x068, 1, 10) 83 #define GEN_SW_1P_TX DSI_HOST_BITS(0x068, 1, 9) 84 #define GEN_SW_0P_TX DSI_HOST_BITS(0x068, 1, 8) 85 #define ACK_RQST_EN DSI_HOST_BITS(0x068, 1, 1) 86 #define TEAR_FX_EN DSI_HOST_BITS(0x068, 1, 0) 87 #define GEN_WC_MSBYTE DSI_HOST_BITS(0x06c, 14, 16) 88 #define GEN_WC_LSBYTE DSI_HOST_BITS(0x06c, 8, 8) 89 #define GEN_VC DSI_HOST_BITS(0x06c, 2, 6) 90 #define GEN_DT DSI_HOST_BITS(0x06c, 6, 0) 91 #define GEN_PLD_DATA DSI_HOST_BITS(0x070, 32, 0) 92 #define GEN_RD_CMD_BUSY DSI_HOST_BITS(0x074, 1, 6) 93 #define GEN_PLD_R_FULL DSI_HOST_BITS(0x074, 1, 5) 94 #define GEN_PLD_R_EMPTY DSI_HOST_BITS(0x074, 1, 4) 95 #define GEN_PLD_W_FULL DSI_HOST_BITS(0x074, 1, 3) 96 #define GEN_PLD_W_EMPTY DSI_HOST_BITS(0x074, 1, 2) 97 #define GEN_CMD_FULL DSI_HOST_BITS(0x074, 1, 1) 98 #define GEN_CMD_EMPTY DSI_HOST_BITS(0x074, 1, 0) 99 #define HSTX_TO_CNT DSI_HOST_BITS(0x078, 16, 16) 100 #define LPRX_TO_CNT DSI_HOST_BITS(0x078, 16, 0) 101 #define HS_RD_TO_CNT DSI_HOST_BITS(0x07c, 16, 0) 102 #define LP_RD_TO_CNT DSI_HOST_BITS(0x080, 16, 0) 103 #define PRESP_TO_MODE DSI_HOST_BITS(0x084, 1, 24) 104 #define HS_WR_TO_CNT DSI_HOST_BITS(0x084, 16, 0) 105 #define LP_WR_TO_CNT DSI_HOST_BITS(0x088, 16, 0) 106 #define BTA_TO_CNT DSI_HOST_BITS(0x08c, 16, 0) 107 #define AUTO_CLKLANE_CTRL DSI_HOST_BITS(0x094, 1, 1) 108 #define PHY_TXREQUESTCLKHS DSI_HOST_BITS(0x094, 1, 0) 109 #define PHY_HS2LP_TIME_CLK_LANE DSI_HOST_BITS(0x098, 10, 16) 110 #define PHY_HS2HS_TIME_CLK_LANE DSI_HOST_BITS(0x098, 10, 0) 111 #define PHY_HS2LP_TIME DSI_HOST_BITS(0x09c, 8, 24) 112 #define PHY_LP2HS_TIME DSI_HOST_BITS(0x09c, 8, 16) 113 #define MAX_RD_TIME DSI_HOST_BITS(0x09c, 15, 0) 114 #define PHY_FORCEPLL DSI_HOST_BITS(0x0a0, 1, 3) 115 #define PHY_ENABLECLK DSI_HOST_BITS(0x0a0, 1, 2) 116 #define PHY_RSTZ DSI_HOST_BITS(0x0a0, 1, 1) 117 #define PHY_SHUTDOWNZ DSI_HOST_BITS(0x0a0, 1, 0) 118 #define PHY_STOP_WAIT_TIME DSI_HOST_BITS(0x0a4, 8, 8) 119 #define N_LANES DSI_HOST_BITS(0x0a4, 2, 0) 120 #define PHY_TXEXITULPSLAN DSI_HOST_BITS(0x0a8, 1, 3) 121 #define PHY_TXREQULPSLAN DSI_HOST_BITS(0x0a8, 1, 2) 122 #define PHY_TXEXITULPSCLK DSI_HOST_BITS(0x0a8, 1, 1) 123 #define PHY_TXREQULPSCLK DSI_HOST_BITS(0x0a8, 1, 0) 124 #define PHY_TX_TRIGGERS DSI_HOST_BITS(0x0ac, 4, 0) 125 #define PHYSTOPSTATECLKLANE DSI_HOST_BITS(0x0b0, 1, 2) 126 #define PHYLOCK DSI_HOST_BITS(0x0b0, 1, 0) 127 #define PHY_TESTCLK DSI_HOST_BITS(0x0b4, 1, 1) 128 #define PHY_TESTCLR DSI_HOST_BITS(0x0b4, 1, 0) 129 #define PHY_TESTEN DSI_HOST_BITS(0x0b8, 1, 16) 130 #define PHY_TESTDOUT DSI_HOST_BITS(0x0b8, 8, 8) 131 #define PHY_TESTDIN DSI_HOST_BITS(0x0b8, 8, 0) 132 #define PHY_TEST_CTRL1 DSI_HOST_BITS(0x0b8, 17, 0) 133 #define PHY_TEST_CTRL0 DSI_HOST_BITS(0x0b4, 2, 0) 134 #define INT_ST0 DSI_HOST_BITS(0x0bc, 21, 0) 135 #define INT_ST1 DSI_HOST_BITS(0x0c0, 18, 0) 136 #define INT_MKS0 DSI_HOST_BITS(0x0c4, 21, 0) 137 #define INT_MKS1 DSI_HOST_BITS(0x0c8, 18, 0) 138 #define INT_FORCE0 DSI_HOST_BITS(0x0d8, 21, 0) 139 #define INT_FORCE1 DSI_HOST_BITS(0x0dc, 18, 0) 140 141 #define CODE_HS_RX_CLOCK 0x34 142 #define CODE_HS_RX_LANE0 0x44 143 #define CODE_HS_RX_LANE1 0x54 144 #define CODE_HS_RX_LANE2 0x84 145 #define CODE_HS_RX_LANE3 0x94 146 147 #define CODE_PLL_VCORANGE_VCOCAP 0x10 148 #define CODE_PLL_CPCTRL 0x11 149 #define CODE_PLL_LPF_CP 0x12 150 #define CODE_PLL_INPUT_DIV_RAT 0x17 151 #define CODE_PLL_LOOP_DIV_RAT 0x18 152 #define CODE_PLL_INPUT_LOOP_DIV_RAT 0x19 153 #define CODE_BANDGAP_BIAS_CTRL 0x20 154 #define CODE_TERMINATION_CTRL 0x21 155 #define CODE_AFE_BIAS_BANDGAP_ANOLOG 0x22 156 157 #define CODE_HSTXDATALANEREQUSETSTATETIME 0x70 158 #define CODE_HSTXDATALANEPREPARESTATETIME 0x71 159 #define CODE_HSTXDATALANEHSZEROSTATETIME 0x72 160 161 /* Transmission mode between vop and MIPI controller */ 162 enum vid_mode_type_t { 163 NON_BURST_SYNC_PLUSE = 0, 164 NON_BURST_SYNC_EVENT, 165 BURST_MODE, 166 }; 167 168 enum cmd_video_mode { 169 VIDEO_MODE = 0, 170 CMD_MODE, 171 }; 172 173 /* Indicate MIPI DSI color mode */ 174 enum dpi_color_coding { 175 DPI_16BIT_CFG_1 = 0, 176 DPI_16BIT_CFG_2, 177 DPI_16BIT_CFG_3, 178 DPI_18BIT_CFG_1, 179 DPI_18BIT_CFG_2, 180 DPI_24BIT, 181 DPI_20BIT_YCBCR_422_LP, 182 DPI_24BIT_YCBCR_422, 183 DPI_16BIT_YCBCR_422, 184 DPI_30BIT, 185 DPI_36BIT, 186 DPI_12BIT_YCBCR_420, 187 }; 188 189 /* Indicate which VOP the MIPI DSI use, bit or little one */ 190 enum vop_id { 191 VOP_B = 0, 192 VOP_L, 193 }; 194 195 #endif /* end of ROCKCHIP_MIPI_DSI_H */ 196