1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 27f4fd26bSSimon Glass /* 37f4fd26bSSimon Glass * Copyright (c) 2015 Google, Inc 47f4fd26bSSimon Glass * 57f4fd26bSSimon Glass * Copyright 2014 Rockchip Inc. 67f4fd26bSSimon Glass */ 77f4fd26bSSimon Glass 87f4fd26bSSimon Glass #ifndef _ASM_ARCH_PMU_RK3288_H 97f4fd26bSSimon Glass #define _ASM_ARCH_PMU_RK3288_H 107f4fd26bSSimon Glass 117f4fd26bSSimon Glass struct rk3288_pmu { 127f4fd26bSSimon Glass u32 wakeup_cfg[2]; 137f4fd26bSSimon Glass u32 pwrdn_con; 147f4fd26bSSimon Glass u32 pwrdn_st; 157f4fd26bSSimon Glass 167f4fd26bSSimon Glass u32 idle_req; 177f4fd26bSSimon Glass u32 idle_st; 187f4fd26bSSimon Glass u32 pwrmode_con; 197f4fd26bSSimon Glass u32 pwr_state; 207f4fd26bSSimon Glass 217f4fd26bSSimon Glass u32 osc_cnt; 227f4fd26bSSimon Glass u32 pll_cnt; 237f4fd26bSSimon Glass u32 stabl_cnt; 247f4fd26bSSimon Glass u32 ddr0io_pwron_cnt; 257f4fd26bSSimon Glass 267f4fd26bSSimon Glass u32 ddr1io_pwron_cnt; 277f4fd26bSSimon Glass u32 core_pwrdn_cnt; 287f4fd26bSSimon Glass u32 core_pwrup_cnt; 297f4fd26bSSimon Glass u32 gpu_pwrdn_cnt; 307f4fd26bSSimon Glass 317f4fd26bSSimon Glass u32 gpu_pwrup_cnt; 327f4fd26bSSimon Glass u32 wakeup_rst_clr_cnt; 337f4fd26bSSimon Glass u32 sft_con; 347f4fd26bSSimon Glass u32 ddr_sref_st; 357f4fd26bSSimon Glass 367f4fd26bSSimon Glass u32 int_con; 377f4fd26bSSimon Glass u32 int_st; 387f4fd26bSSimon Glass u32 boot_addr_sel; 397f4fd26bSSimon Glass u32 grf_con; 407f4fd26bSSimon Glass 417f4fd26bSSimon Glass u32 gpio_sr; 427f4fd26bSSimon Glass u32 gpio0pull[3]; 437f4fd26bSSimon Glass 447f4fd26bSSimon Glass u32 gpio0drv[3]; 457f4fd26bSSimon Glass u32 gpio_op; 467f4fd26bSSimon Glass 477f4fd26bSSimon Glass u32 gpio0_sel18; /* 0x80 */ 48a4275f5eSSimon Glass u32 gpio0_iomux[4]; /* a, b, c, d */ 497f4fd26bSSimon Glass u32 sys_reg[4]; 507f4fd26bSSimon Glass }; 517f4fd26bSSimon Glass check_member(rk3288_pmu, sys_reg[3], 0x00a0); 527f4fd26bSSimon Glass 53a4275f5eSSimon Glass enum { 54a4275f5eSSimon Glass PMU_GPIO0_A = 0, 55a4275f5eSSimon Glass PMU_GPIO0_B, 56a4275f5eSSimon Glass PMU_GPIO0_C, 57a4275f5eSSimon Glass PMU_GPIO0_D, 58a4275f5eSSimon Glass }; 59a4275f5eSSimon Glass 607f4fd26bSSimon Glass /* PMU_GPIO0_B_IOMUX */ 617f4fd26bSSimon Glass enum { 627f4fd26bSSimon Glass GPIO0_B7_SHIFT = 14, 637f4fd26bSSimon Glass GPIO0_B7_MASK = 1, 647f4fd26bSSimon Glass GPIO0_B7_GPIOB7 = 0, 657f4fd26bSSimon Glass GPIO0_B7_I2C0PMU_SDA, 667f4fd26bSSimon Glass 677f4fd26bSSimon Glass GPIO0_B5_SHIFT = 10, 687f4fd26bSSimon Glass GPIO0_B5_MASK = 1, 697f4fd26bSSimon Glass GPIO0_B5_GPIOB5 = 0, 707f4fd26bSSimon Glass GPIO0_B5_CLK_27M, 717f4fd26bSSimon Glass 727f4fd26bSSimon Glass GPIO0_B2_SHIFT = 4, 737f4fd26bSSimon Glass GPIO0_B2_MASK = 1, 747f4fd26bSSimon Glass GPIO0_B2_GPIOB2 = 0, 757f4fd26bSSimon Glass GPIO0_B2_TSADC_INT, 767f4fd26bSSimon Glass }; 777f4fd26bSSimon Glass 787f4fd26bSSimon Glass /* PMU_GPIO0_C_IOMUX */ 797f4fd26bSSimon Glass enum { 807f4fd26bSSimon Glass GPIO0_C1_SHIFT = 2, 817f4fd26bSSimon Glass GPIO0_C1_MASK = 3, 827f4fd26bSSimon Glass GPIO0_C1_GPIOC1 = 0, 837f4fd26bSSimon Glass GPIO0_C1_TEST_CLKOUT, 847f4fd26bSSimon Glass GPIO0_C1_CLKT1_27M, 857f4fd26bSSimon Glass 867f4fd26bSSimon Glass GPIO0_C0_SHIFT = 0, 877f4fd26bSSimon Glass GPIO0_C0_MASK = 1, 887f4fd26bSSimon Glass GPIO0_C0_GPIOC0 = 0, 897f4fd26bSSimon Glass GPIO0_C0_I2C0PMU_SCL, 907f4fd26bSSimon Glass }; 917f4fd26bSSimon Glass 927f4fd26bSSimon Glass #endif 93