1 /* 2 * (C) Copyright 2012 SAMSUNG Electronics 3 * Jaehoon Chung <jh80.chung@samsung.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __ASM_ARCH_I2C_H 9 #define __ASM_ARCH_I2C_H 10 11 struct i2c_regs { 12 u32 con; 13 u32 clkdiv; 14 u32 mrxaddr; 15 u32 mrxraddr; 16 u32 mtxcnt; 17 u32 mrxcnt; 18 u32 ien; 19 u32 ipd; 20 u32 fcnt; 21 u32 reserved0[0x37]; 22 u32 txdata[8]; 23 u32 reserved1[0x38]; 24 u32 rxdata[8]; 25 }; 26 27 /* Control register */ 28 #define I2C_CON_EN (1 << 0) 29 #define I2C_CON_MOD(mod) ((mod) << 1) 30 #define I2C_MODE_TX 0x00 31 #define I2C_MODE_TRX 0x01 32 #define I2C_MODE_RX 0x02 33 #define I2C_MODE_RRX 0x03 34 #define I2C_CON_MASK (3 << 1) 35 36 #define I2C_CON_START (1 << 3) 37 #define I2C_CON_STOP (1 << 4) 38 #define I2C_CON_LASTACK (1 << 5) 39 #define I2C_CON_ACTACK (1 << 6) 40 41 /* Clock dividor register */ 42 #define I2C_CLKDIV_VAL(divl, divh) \ 43 (((divl) & 0xffff) | (((divh) << 16) & 0xffff0000)) 44 45 /* the slave address accessed for master rx mode */ 46 #define I2C_MRXADDR_SET(vld, addr) (((vld) << 24) | (addr)) 47 48 /* the slave register address accessed for master rx mode */ 49 #define I2C_MRXRADDR_SET(vld, raddr) (((vld) << 24) | (raddr)) 50 51 /* interrupt enable register */ 52 #define I2C_BTFIEN (1 << 0) 53 #define I2C_BRFIEN (1 << 1) 54 #define I2C_MBTFIEN (1 << 2) 55 #define I2C_MBRFIEN (1 << 3) 56 #define I2C_STARTIEN (1 << 4) 57 #define I2C_STOPIEN (1 << 5) 58 #define I2C_NAKRCVIEN (1 << 6) 59 60 /* interrupt pending register */ 61 #define I2C_BTFIPD (1 << 0) 62 #define I2C_BRFIPD (1 << 1) 63 #define I2C_MBTFIPD (1 << 2) 64 #define I2C_MBRFIPD (1 << 3) 65 #define I2C_STARTIPD (1 << 4) 66 #define I2C_STOPIPD (1 << 5) 67 #define I2C_NAKRCVIPD (1 << 6) 68 #define I2C_IPD_ALL_CLEAN 0x7f 69 70 #endif 71