1 /*
2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __SOC_ROCKCHIP_RK3399_GRF_H__
8 #define __SOC_ROCKCHIP_RK3399_GRF_H__
9 
10 struct rk3399_grf_regs {
11 	u32 reserved[0x800];
12 	u32 usb3_perf_con0;
13 	u32 usb3_perf_con1;
14 	u32 usb3_perf_con2;
15 	u32 usb3_perf_rd_max_latency_num;
16 	u32 usb3_perf_rd_latency_samp_num;
17 	u32 usb3_perf_rd_latency_acc_num;
18 	u32 usb3_perf_rd_axi_total_byte;
19 	u32 usb3_perf_wr_axi_total_byte;
20 	u32 usb3_perf_working_cnt;
21 	u32 reserved1[0x103];
22 	u32 usb3otg0_con0;
23 	u32 usb3otg0_con1;
24 	u32 reserved2[2];
25 	u32 usb3otg1_con0;
26 	u32 usb3otg1_con1;
27 	u32 reserved3[2];
28 	u32 usb3otg0_status_lat0;
29 	u32 usb3otg0_status_lat1;
30 	u32 usb3otg0_status_cb;
31 	u32 reserved4;
32 	u32 usb3otg1_status_lat0;
33 	u32 usb3otg1_status_lat1;
34 	u32 usb3ogt1_status_cb;
35 	u32 reserved5[0x6e5];
36 	u32 pcie_perf_con0;
37 	u32 pcie_perf_con1;
38 	u32 pcie_perf_con2;
39 	u32 pcie_perf_rd_max_latency_num;
40 	u32 pcie_perf_rd_latency_samp_num;
41 	u32 pcie_perf_rd_laterncy_acc_num;
42 	u32 pcie_perf_rd_axi_total_byte;
43 	u32 pcie_perf_wr_axi_total_byte;
44 	u32 pcie_perf_working_cnt;
45 	u32 reserved6[0x37];
46 	u32 usb20_host0_con0;
47 	u32 usb20_host0_con1;
48 	u32 reserved7[2];
49 	u32 usb20_host1_con0;
50 	u32 usb20_host1_con1;
51 	u32 reserved8[2];
52 	u32 hsic_con0;
53 	u32 hsic_con1;
54 	u32 reserved9[6];
55 	u32 grf_usbhost0_status;
56 	u32 grf_usbhost1_Status;
57 	u32 grf_hsic_status;
58 	u32 reserved10[0xc9];
59 	u32 hsicphy_con0;
60 	u32 reserved11[3];
61 	u32 usbphy0_ctrl[26];
62 	u32 reserved12[6];
63 	u32 usbphy1[26];
64 	u32 reserved13[0x72f];
65 	u32 soc_con9;
66 	u32 reserved14[0x0a];
67 	u32 soc_con20;
68 	u32 soc_con21;
69 	u32 soc_con22;
70 	u32 soc_con23;
71 	u32 soc_con24;
72 	u32 soc_con25;
73 	u32 soc_con26;
74 	u32 reserved15[0xf65];
75 	u32 cpu_con[4];
76 	u32 reserved16[0x1c];
77 	u32 cpu_status[6];
78 	u32 reserved17[0x1a];
79 	u32 a53_perf_con[4];
80 	u32 a53_perf_rd_mon_st;
81 	u32 a53_perf_rd_mon_end;
82 	u32 a53_perf_wr_mon_st;
83 	u32 a53_perf_wr_mon_end;
84 	u32 a53_perf_rd_max_latency_num;
85 	u32 a53_perf_rd_latency_samp_num;
86 	u32 a53_perf_rd_laterncy_acc_num;
87 	u32 a53_perf_rd_axi_total_byte;
88 	u32 a53_perf_wr_axi_total_byte;
89 	u32 a53_perf_working_cnt;
90 	u32 a53_perf_int_status;
91 	u32 reserved18[0x31];
92 	u32 a72_perf_con[4];
93 	u32 a72_perf_rd_mon_st;
94 	u32 a72_perf_rd_mon_end;
95 	u32 a72_perf_wr_mon_st;
96 	u32 a72_perf_wr_mon_end;
97 	u32 a72_perf_rd_max_latency_num;
98 	u32 a72_perf_rd_latency_samp_num;
99 	u32 a72_perf_rd_laterncy_acc_num;
100 	u32 a72_perf_rd_axi_total_byte;
101 	u32 a72_perf_wr_axi_total_byte;
102 	u32 a72_perf_working_cnt;
103 	u32 a72_perf_int_status;
104 	u32 reserved19[0x7f6];
105 	u32 soc_con5;
106 	u32 soc_con6;
107 	u32 reserved20[0x779];
108 	u32 gpio2a_iomux;
109 	union {
110 		u32 iomux_spi2;
111 		u32 gpio2b_iomux;
112 	};
113 	union {
114 		u32 gpio2c_iomux;
115 		u32 iomux_spi5;
116 	};
117 	u32 gpio2d_iomux;
118 	union {
119 		u32 gpio3a_iomux;
120 		u32 iomux_spi0;
121 	};
122 	u32 gpio3b_iomux;
123 	u32 gpio3c_iomux;
124 	union {
125 		u32 iomux_i2s0;
126 		u32 gpio3d_iomux;
127 	};
128 	union {
129 		u32 iomux_i2sclk;
130 		u32 gpio4a_iomux;
131 	};
132 	union {
133 		u32 iomux_sdmmc;
134 		u32 iomux_uart2a;
135 		u32 gpio4b_iomux;
136 	};
137 	union {
138 		u32 iomux_pwm_0;
139 		u32 iomux_pwm_1;
140 		u32 iomux_uart2b;
141 		u32 iomux_uart2c;
142 		u32 iomux_edp_hotplug;
143 		u32 gpio4c_iomux;
144 	};
145 	u32 gpio4d_iomux;
146 	u32 reserved21[4];
147 	u32 gpio2_p[4];
148 	u32 gpio3_p[4];
149 	u32 gpio4_p[4];
150 	u32 reserved22[4];
151 	u32 gpio2_sr[3][4];
152 	u32 reserved23[4];
153 	u32 gpio2_smt[3][4];
154 	u32 reserved24[(0xe100 - 0xe0ec)/4 - 1];
155 	u32 gpio2_e[4];
156 	u32 gpio3_e[7];
157 	u32 gpio4_e[5];
158 	u32 reserved24a[(0xe200 - 0xe13c)/4 - 1];
159 	u32 soc_con0;
160 	u32 soc_con1;
161 	u32 soc_con2;
162 	u32 soc_con3;
163 	u32 soc_con4;
164 	u32 soc_con5_pcie;
165 	u32 reserved25;
166 	u32 soc_con7;
167 	u32 soc_con8;
168 	u32 soc_con9_pcie;
169 	u32 reserved26[0x1e];
170 	u32 soc_status[6];
171 	u32 reserved27[0x32];
172 	u32 ddrc0_con0;
173 	u32 ddrc0_con1;
174 	u32 ddrc1_con0;
175 	u32 ddrc1_con1;
176 	u32 reserved28[0xac];
177 	u32 io_vsel;
178 	u32 saradc_testbit;
179 	u32 tsadc_testbit_l;
180 	u32 tsadc_testbit_h;
181 	u32 reserved29[0x6c];
182 	u32 chip_id_addr;
183 	u32 reserved30[0x1f];
184 	u32 fast_boot_addr;
185 	u32 reserved31[0x1df];
186 	u32 emmccore_con[12];
187 	u32 reserved32[4];
188 	u32 emmccore_status[4];
189 	u32 reserved33[0x1cc];
190 	u32 emmcphy_con[7];
191 	u32 reserved34;
192 	u32 emmcphy_status;
193 };
194 check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
195 
196 struct rk3399_pmugrf_regs {
197 	union {
198 		u32 iomux_pwm_3a;
199 		u32 gpio0a_iomux;
200 	};
201 	u32 gpio0b_iomux;
202 	u32 reserved0[2];
203 	union {
204 		u32 spi1_rxd;
205 		u32 tsadc_int;
206 		u32 gpio1a_iomux;
207 	};
208 	union {
209 		u32 spi1_csclktx;
210 		u32 iomux_pwm_3b;
211 		u32 iomux_i2c0_sda;
212 		u32 gpio1b_iomux;
213 	};
214 	union {
215 		u32 iomux_pwm_2;
216 		u32 iomux_i2c0_scl;
217 		u32 gpio1c_iomux;
218 	};
219 	u32 gpio1d_iomux;
220 	u32 reserved1[8];
221 	u32 gpio0_p[2];
222 	u32 reserved2[2];
223 	u32 gpio1_p[4];
224 	u32 reserved3[8];
225 	u32 gpio0a_e;
226 	u32 reserved4;
227 	u32 gpio0b_e;
228 	u32 reserved5[5];
229 	u32 gpio1a_e;
230 	u32 reserved6;
231 	u32 gpio1b_e;
232 	u32 reserved7;
233 	u32 gpio1c_e;
234 	u32 reserved8;
235 	u32 gpio1d_e;
236 	u32 reserved9[0x11];
237 	u32 gpio0l_sr;
238 	u32 reserved10;
239 	u32 gpio1l_sr;
240 	u32 gpio1h_sr;
241 	u32 reserved11[4];
242 	u32 gpio0a_smt;
243 	u32 gpio0b_smt;
244 	u32 reserved12[2];
245 	u32 gpio1a_smt;
246 	u32 gpio1b_smt;
247 	u32 gpio1c_smt;
248 	u32 gpio1d_smt;
249 	u32 reserved13[8];
250 	u32 gpio0l_he;
251 	u32 reserved14;
252 	u32 gpio1l_he;
253 	u32 gpio1h_he;
254 	u32 reserved15[4];
255 	u32 soc_con0;
256 	u32 reserved16[9];
257 	u32 soc_con10;
258 	u32 soc_con11;
259 	u32 reserved17[0x24];
260 	u32 pmupvtm_con0;
261 	u32 pmupvtm_con1;
262 	u32 pmupvtm_status0;
263 	u32 pmupvtm_status1;
264 	u32 grf_osc_e;
265 	u32 reserved18[0x2b];
266 	u32 os_reg0;
267 	u32 os_reg1;
268 	u32 os_reg2;
269 	u32 os_reg3;
270 };
271 check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
272 
273 struct rk3399_pmusgrf_regs {
274 	u32 ddr_rgn_con[35];
275 	u32 reserved[0x1fe5];
276 	u32 soc_con8;
277 	u32 soc_con9;
278 	u32 soc_con10;
279 	u32 soc_con11;
280 	u32 soc_con12;
281 	u32 soc_con13;
282 	u32 soc_con14;
283 	u32 soc_con15;
284 	u32 reserved1[3];
285 	u32 soc_con19;
286 	u32 soc_con20;
287 	u32 soc_con21;
288 	u32 soc_con22;
289 	u32 reserved2[0x29];
290 	u32 perilp_con[9];
291 	u32 reserved4[7];
292 	u32 perilp_status;
293 	u32 reserved5[0xfaf];
294 	u32 soc_con0;
295 	u32 soc_con1;
296 	u32 reserved6[0x3e];
297 	u32 pmu_con[9];
298 	u32 reserved7[0x17];
299 	u32 fast_boot_addr;
300 	u32 reserved8[0x1f];
301 	u32 efuse_prg_mask;
302 	u32 efuse_read_mask;
303 	u32 reserved9[0x0e];
304 	u32 pmu_slv_con0;
305 	u32 pmu_slv_con1;
306 	u32 reserved10[0x771];
307 	u32 soc_con3;
308 	u32 soc_con4;
309 	u32 soc_con5;
310 	u32 soc_con6;
311 	u32 soc_con7;
312 	u32 reserved11[8];
313 	u32 soc_con16;
314 	u32 soc_con17;
315 	u32 soc_con18;
316 	u32 reserved12[0xdd];
317 	u32 slv_secure_con0;
318 	u32 slv_secure_con1;
319 	u32 reserved13;
320 	u32 slv_secure_con2;
321 	u32 slv_secure_con3;
322 	u32 slv_secure_con4;
323 };
324 check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
325 
326 enum {
327 	/* GRF_GPIO2B_IOMUX */
328 	GRF_GPIO2B1_SEL_SHIFT	= 0,
329 	GRF_GPIO2B1_SEL_MASK	= 3 << GRF_GPIO2B1_SEL_SHIFT,
330 	GRF_SPI2TPM_RXD		= 1,
331 	GRF_GPIO2B2_SEL_SHIFT	= 2,
332 	GRF_GPIO2B2_SEL_MASK	= 3 << GRF_GPIO2B2_SEL_SHIFT,
333 	GRF_SPI2TPM_TXD		= 1,
334 	GRF_GPIO2B3_SEL_SHIFT	= 6,
335 	GRF_GPIO2B3_SEL_MASK	= 3 << GRF_GPIO2B3_SEL_SHIFT,
336 	GRF_SPI2TPM_CLK		= 1,
337 	GRF_GPIO2B4_SEL_SHIFT	= 8,
338 	GRF_GPIO2B4_SEL_MASK	= 3 << GRF_GPIO2B4_SEL_SHIFT,
339 	GRF_SPI2TPM_CSN0	= 1,
340 
341 	/* GRF_GPIO2C_IOMUX */
342 	GRF_GPIO2C0_SEL_SHIFT   = 0,
343 	GRF_GPIO2C0_SEL_MASK    = 3 << GRF_GPIO2C0_SEL_SHIFT,
344 	GRF_UART0BT_SIN         = 1,
345 	GRF_GPIO2C1_SEL_SHIFT   = 2,
346 	GRF_GPIO2C1_SEL_MASK    = 3 << GRF_GPIO2C1_SEL_SHIFT,
347 	GRF_UART0BT_SOUT        = 1,
348 	GRF_GPIO2C4_SEL_SHIFT   = 8,
349 	GRF_GPIO2C4_SEL_MASK    = 3 << GRF_GPIO2C4_SEL_SHIFT,
350 	GRF_SPI5EXPPLUS_RXD     = 2,
351 	GRF_GPIO2C5_SEL_SHIFT   = 10,
352 	GRF_GPIO2C5_SEL_MASK    = 3 << GRF_GPIO2C5_SEL_SHIFT,
353 	GRF_SPI5EXPPLUS_TXD     = 2,
354 	GRF_GPIO2C6_SEL_SHIFT   = 12,
355 	GRF_GPIO2C6_SEL_MASK    = 3 << GRF_GPIO2C6_SEL_SHIFT,
356 	GRF_SPI5EXPPLUS_CLK     = 2,
357 	GRF_GPIO2C7_SEL_SHIFT   = 14,
358 	GRF_GPIO2C7_SEL_MASK    = 3 << GRF_GPIO2C7_SEL_SHIFT,
359 	GRF_SPI5EXPPLUS_CSN0    = 2,
360 
361 	/* GRF_GPIO3A_IOMUX */
362 	GRF_GPIO3A0_SEL_SHIFT   = 0,
363 	GRF_GPIO3A0_SEL_MASK    = 3 << GRF_GPIO3A0_SEL_SHIFT,
364 	GRF_MAC_TXD2            = 1,
365 	GRF_GPIO3A1_SEL_SHIFT   = 2,
366 	GRF_GPIO3A1_SEL_MASK    = 3 << GRF_GPIO3A1_SEL_SHIFT,
367 	GRF_MAC_TXD3            = 1,
368 	GRF_GPIO3A2_SEL_SHIFT   = 4,
369 	GRF_GPIO3A2_SEL_MASK    = 3 << GRF_GPIO3A2_SEL_SHIFT,
370 	GRF_MAC_RXD2            = 1,
371 	GRF_GPIO3A3_SEL_SHIFT   = 6,
372 	GRF_GPIO3A3_SEL_MASK    = 3 << GRF_GPIO3A3_SEL_SHIFT,
373 	GRF_MAC_RXD3            = 1,
374 	GRF_GPIO3A4_SEL_SHIFT	= 8,
375 	GRF_GPIO3A4_SEL_MASK	= 3 << GRF_GPIO3A4_SEL_SHIFT,
376 	GRF_MAC_TXD0            = 1,
377 	GRF_SPI0NORCODEC_RXD	= 2,
378 	GRF_GPIO3A5_SEL_SHIFT	= 10,
379 	GRF_GPIO3A5_SEL_MASK	= 3 << GRF_GPIO3A5_SEL_SHIFT,
380 	GRF_MAC_TXD1            = 1,
381 	GRF_SPI0NORCODEC_TXD	= 2,
382 	GRF_GPIO3A6_SEL_SHIFT	= 12,
383 	GRF_GPIO3A6_SEL_MASK	= 3 << GRF_GPIO3A6_SEL_SHIFT,
384 	GRF_MAC_RXD0            = 1,
385 	GRF_SPI0NORCODEC_CLK	= 2,
386 	GRF_GPIO3A7_SEL_SHIFT	= 14,
387 	GRF_GPIO3A7_SEL_MASK	= 3 << GRF_GPIO3A7_SEL_SHIFT,
388 	GRF_MAC_RXD1            = 1,
389 	GRF_SPI0NORCODEC_CSN0	= 2,
390 
391 	/* GRF_GPIO3B_IOMUX */
392 	GRF_GPIO3B0_SEL_SHIFT	= 0,
393 	GRF_GPIO3B0_SEL_MASK	= 3 << GRF_GPIO3B0_SEL_SHIFT,
394 	GRF_MAC_MDC             = 1,
395 	GRF_SPI0NORCODEC_CSN1	= 2,
396 	GRF_GPIO3B1_SEL_SHIFT	= 2,
397 	GRF_GPIO3B1_SEL_MASK	= 3 << GRF_GPIO3B1_SEL_SHIFT,
398 	GRF_MAC_RXDV            = 1,
399 	GRF_GPIO3B3_SEL_SHIFT	= 6,
400 	GRF_GPIO3B3_SEL_MASK	= 3 << GRF_GPIO3B3_SEL_SHIFT,
401 	GRF_MAC_CLK             = 1,
402 	GRF_GPIO3B4_SEL_SHIFT	= 8,
403 	GRF_GPIO3B4_SEL_MASK	= 3 << GRF_GPIO3B4_SEL_SHIFT,
404 	GRF_MAC_TXEN            = 1,
405 	GRF_GPIO3B5_SEL_SHIFT	= 10,
406 	GRF_GPIO3B5_SEL_MASK	= 3 << GRF_GPIO3B5_SEL_SHIFT,
407 	GRF_MAC_MDIO            = 1,
408 	GRF_GPIO3B6_SEL_SHIFT   = 12,
409 	GRF_GPIO3B6_SEL_MASK    = 3 << GRF_GPIO3B6_SEL_SHIFT,
410 	GRF_MAC_RXCLK           = 1,
411 
412 	/* GRF_GPIO3C_IOMUX */
413 	GRF_GPIO3C1_SEL_SHIFT	= 2,
414 	GRF_GPIO3C1_SEL_MASK	= 3 << GRF_GPIO3C1_SEL_SHIFT,
415 	GRF_MAC_TXCLK           = 1,
416 
417 	/* GRF_GPIO4B_IOMUX */
418 	GRF_GPIO4B0_SEL_SHIFT	= 0,
419 	GRF_GPIO4B0_SEL_MASK	= 3 << GRF_GPIO4B0_SEL_SHIFT,
420 	GRF_SDMMC_DATA0		= 1,
421 	GRF_UART2DBGA_SIN	= 2,
422 	GRF_GPIO4B1_SEL_SHIFT	= 2,
423 	GRF_GPIO4B1_SEL_MASK	= 3 << GRF_GPIO4B1_SEL_SHIFT,
424 	GRF_SDMMC_DATA1		= 1,
425 	GRF_UART2DBGA_SOUT	= 2,
426 	GRF_GPIO4B2_SEL_SHIFT	= 4,
427 	GRF_GPIO4B2_SEL_MASK	= 3 << GRF_GPIO4B2_SEL_SHIFT,
428 	GRF_SDMMC_DATA2		= 1,
429 	GRF_GPIO4B3_SEL_SHIFT	= 6,
430 	GRF_GPIO4B3_SEL_MASK	= 3 << GRF_GPIO4B3_SEL_SHIFT,
431 	GRF_SDMMC_DATA3		= 1,
432 	GRF_GPIO4B4_SEL_SHIFT	= 8,
433 	GRF_GPIO4B4_SEL_MASK    = 3 << GRF_GPIO4B4_SEL_SHIFT,
434 	GRF_SDMMC_CLKOUT        = 1,
435 	GRF_GPIO4B5_SEL_SHIFT   = 10,
436 	GRF_GPIO4B5_SEL_MASK    = 3 << GRF_GPIO4B5_SEL_SHIFT,
437 	GRF_SDMMC_CMD           = 1,
438 
439 	/*  GRF_GPIO4C_IOMUX */
440 	GRF_GPIO4C0_SEL_SHIFT   = 0,
441 	GRF_GPIO4C0_SEL_MASK    = 3 << GRF_GPIO4C0_SEL_SHIFT,
442 	GRF_UART2DGBB_SIN       = 2,
443 	GRF_HDMII2C_SCL         = 3,
444 	GRF_GPIO4C1_SEL_SHIFT   = 2,
445 	GRF_GPIO4C1_SEL_MASK    = 3 << GRF_GPIO4C1_SEL_SHIFT,
446 	GRF_UART2DGBB_SOUT      = 2,
447 	GRF_HDMII2C_SDA         = 3,
448 	GRF_GPIO4C2_SEL_SHIFT   = 4,
449 	GRF_GPIO4C2_SEL_MASK    = 3 << GRF_GPIO4C2_SEL_SHIFT,
450 	GRF_PWM_0               = 1,
451 	GRF_GPIO4C3_SEL_SHIFT   = 6,
452 	GRF_GPIO4C3_SEL_MASK    = 3 << GRF_GPIO4C3_SEL_SHIFT,
453 	GRF_UART2DGBC_SIN       = 1,
454 	GRF_GPIO4C4_SEL_SHIFT   = 8,
455 	GRF_GPIO4C4_SEL_MASK    = 3 << GRF_GPIO4C4_SEL_SHIFT,
456 	GRF_UART2DBGC_SOUT      = 1,
457 	GRF_GPIO4C6_SEL_SHIFT   = 12,
458 	GRF_GPIO4C6_SEL_MASK    = 3 << GRF_GPIO4C6_SEL_SHIFT,
459 	GRF_PWM_1               = 1,
460 
461 	/* GRF_GPIO3A_E01 */
462 	GRF_GPIO3A0_E_SHIFT = 0,
463 	GRF_GPIO3A0_E_MASK = 7 << GRF_GPIO3A0_E_SHIFT,
464 	GRF_GPIO3A1_E_SHIFT = 3,
465 	GRF_GPIO3A1_E_MASK = 7 << GRF_GPIO3A1_E_SHIFT,
466 	GRF_GPIO3A2_E_SHIFT = 6,
467 	GRF_GPIO3A2_E_MASK = 7 << GRF_GPIO3A2_E_SHIFT,
468 	GRF_GPIO3A3_E_SHIFT = 9,
469 	GRF_GPIO3A3_E_MASK = 7 << GRF_GPIO3A3_E_SHIFT,
470 	GRF_GPIO3A4_E_SHIFT = 12,
471 	GRF_GPIO3A4_E_MASK = 7 << GRF_GPIO3A4_E_SHIFT,
472 	GRF_GPIO3A5_E0_SHIFT = 15,
473 	GRF_GPIO3A5_E0_MASK = 1 << GRF_GPIO3A5_E0_SHIFT,
474 
475 	/*  GRF_GPIO3A_E2 */
476 	GRF_GPIO3A5_E12_SHIFT = 0,
477 	GRF_GPIO3A5_E12_MASK = 3 << GRF_GPIO3A5_E12_SHIFT,
478 	GRF_GPIO3A6_E_SHIFT = 2,
479 	GRF_GPIO3A6_E_MASK = 7 << GRF_GPIO3A6_E_SHIFT,
480 	GRF_GPIO3A7_E_SHIFT = 5,
481 	GRF_GPIO3A7_E_MASK = 7 << GRF_GPIO3A7_E_SHIFT,
482 
483 	/* GRF_GPIO3B_E01 */
484 	GRF_GPIO3B0_E_SHIFT = 0,
485 	GRF_GPIO3B0_E_MASK = 7 << GRF_GPIO3B0_E_SHIFT,
486 	GRF_GPIO3B1_E_SHIFT = 3,
487 	GRF_GPIO3B1_E_MASK = 7 << GRF_GPIO3B1_E_SHIFT,
488 	GRF_GPIO3B2_E_SHIFT = 6,
489 	GRF_GPIO3B2_E_MASK = 7 << GRF_GPIO3B2_E_SHIFT,
490 	GRF_GPIO3B3_E_SHIFT = 9,
491 	GRF_GPIO3B3_E_MASK = 7 << GRF_GPIO3B3_E_SHIFT,
492 	GRF_GPIO3B4_E_SHIFT = 12,
493 	GRF_GPIO3B4_E_MASK = 7 << GRF_GPIO3B4_E_SHIFT,
494 	GRF_GPIO3B5_E0_SHIFT = 15,
495 	GRF_GPIO3B5_E0_MASK = 1 << GRF_GPIO3B5_E0_SHIFT,
496 
497 	/*  GRF_GPIO3A_E2 */
498 	GRF_GPIO3B5_E12_SHIFT = 0,
499 	GRF_GPIO3B5_E12_MASK = 3 << GRF_GPIO3B5_E12_SHIFT,
500 	GRF_GPIO3B6_E_SHIFT = 2,
501 	GRF_GPIO3B6_E_MASK = 7 << GRF_GPIO3B6_E_SHIFT,
502 	GRF_GPIO3B7_E_SHIFT = 5,
503 	GRF_GPIO3B7_E_MASK = 7 << GRF_GPIO3B7_E_SHIFT,
504 
505 	/* GRF_GPIO3C_E01 */
506 	GRF_GPIO3C0_E_SHIFT = 0,
507 	GRF_GPIO3C0_E_MASK = 7 << GRF_GPIO3C0_E_SHIFT,
508 	GRF_GPIO3C1_E_SHIFT = 3,
509 	GRF_GPIO3C1_E_MASK = 7 << GRF_GPIO3C1_E_SHIFT,
510 	GRF_GPIO3C2_E_SHIFT = 6,
511 	GRF_GPIO3C2_E_MASK = 7 << GRF_GPIO3C2_E_SHIFT,
512 	GRF_GPIO3C3_E_SHIFT = 9,
513 	GRF_GPIO3C3_E_MASK = 7 << GRF_GPIO3C3_E_SHIFT,
514 	GRF_GPIO3C4_E_SHIFT = 12,
515 	GRF_GPIO3C4_E_MASK = 7 << GRF_GPIO3C4_E_SHIFT,
516 	GRF_GPIO3C5_E0_SHIFT = 15,
517 	GRF_GPIO3C5_E0_MASK = 1 << GRF_GPIO3C5_E0_SHIFT,
518 
519 	/*  GRF_GPIO3C_E2 */
520 	GRF_GPIO3C5_E12_SHIFT = 0,
521 	GRF_GPIO3C5_E12_MASK = 3 << GRF_GPIO3C5_E12_SHIFT,
522 	GRF_GPIO3C6_E_SHIFT = 2,
523 	GRF_GPIO3C6_E_MASK = 7 << GRF_GPIO3C6_E_SHIFT,
524 	GRF_GPIO3C7_E_SHIFT = 5,
525 	GRF_GPIO3C7_E_MASK = 7 << GRF_GPIO3C7_E_SHIFT,
526 
527 	/* GRF_SOC_CON7 */
528 	GRF_UART_DBG_SEL_SHIFT  = 10,
529 	GRF_UART_DBG_SEL_MASK   = 3 << GRF_UART_DBG_SEL_SHIFT,
530 	GRF_UART_DBG_SEL_C      = 2,
531 
532 	/* GRF_SOC_CON20 */
533 	GRF_DSI0_VOP_SEL_SHIFT  = 0,
534 	GRF_DSI0_VOP_SEL_MASK   = 1 << GRF_DSI0_VOP_SEL_SHIFT,
535 	GRF_DSI0_VOP_SEL_B      = 0,
536 	GRF_DSI0_VOP_SEL_L      = 1,
537 	GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6,
538 	GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6,
539 	GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6,
540 
541 	/* GRF_SOC_CON22 */
542 	GRF_DPHY_TX0_RXMODE_SHIFT = 0,
543 	GRF_DPHY_TX0_RXMODE_MASK  = 0xf << GRF_DPHY_TX0_RXMODE_SHIFT,
544 	GRF_DPHY_TX0_RXMODE_EN    = 0xb,
545 	GRF_DPHY_TX0_RXMODE_DIS   = 0,
546 
547 	GRF_DPHY_TX0_TXSTOPMODE_SHIFT = 4,
548 	GRF_DPHY_TX0_TXSTOPMODE_MASK  = 0xf0 << GRF_DPHY_TX0_TXSTOPMODE_SHIFT,
549 	GRF_DPHY_TX0_TXSTOPMODE_EN    = 0xc,
550 	GRF_DPHY_TX0_TXSTOPMODE_DIS   = 0,
551 
552 	GRF_DPHY_TX0_TURNREQUEST_SHIFT = 12,
553 	GRF_DPHY_TX0_TURNREQUEST_MASK  =
554 		0xf000 << GRF_DPHY_TX0_TURNREQUEST_SHIFT,
555 	GRF_DPHY_TX0_TURNREQUEST_EN    = 0x1,
556 	GRF_DPHY_TX0_TURNREQUEST_DIS   = 0,
557 
558 	/*  PMUGRF_GPIO0A_IOMUX */
559 	PMUGRF_GPIO0A6_SEL_SHIFT        = 12,
560 	PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
561 	PMUGRF_PWM_3A           = 1,
562 
563 	/*  PMUGRF_GPIO1A_IOMUX */
564 	PMUGRF_GPIO1A7_SEL_SHIFT        = 14,
565 	PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
566 	PMUGRF_SPI1EC_RXD       = 2,
567 
568 	/*  PMUGRF_GPIO1B_IOMUX */
569 	PMUGRF_GPIO1B0_SEL_SHIFT        = 0,
570 	PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
571 	PMUGRF_SPI1EC_TXD       = 2,
572 	PMUGRF_GPIO1B1_SEL_SHIFT        = 2,
573 	PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
574 	PMUGRF_SPI1EC_CLK       = 2,
575 	PMUGRF_GPIO1B2_SEL_SHIFT        = 4,
576 	PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
577 	PMUGRF_SPI1EC_CSN0      = 2,
578 	PMUGRF_GPIO1B6_SEL_SHIFT        = 12,
579 	PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
580 	PMUGRF_PWM_3B           = 1,
581 	PMUGRF_GPIO1B7_SEL_SHIFT        = 14,
582 	PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
583 	PMUGRF_I2C0PMU_SDA      = 2,
584 
585 	/*  PMUGRF_GPIO1C_IOMUX */
586 	PMUGRF_GPIO1C0_SEL_SHIFT        = 0,
587 	PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
588 	PMUGRF_I2C0PMU_SCL      = 2,
589 	PMUGRF_GPIO1C3_SEL_SHIFT        = 6,
590 	PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
591 	PMUGRF_PWM_2            = 1,
592 	PMUGRF_GPIO1C4_SEL_SHIFT = 8,
593 	PMUGRF_GPIO1C4_SEL_MASK = 3 << PMUGRF_GPIO1C4_SEL_SHIFT,
594 	PMUGRF_I2C8PMU_SDA = 1,
595 	PMUGRF_GPIO1C5_SEL_SHIFT = 10,
596 	PMUGRF_GPIO1C5_SEL_MASK = 3 << PMUGRF_GPIO1C5_SEL_SHIFT,
597 	PMUGRF_I2C8PMU_SCL = 1,
598 };
599 
600 /* GRF_SOC_CON5 */
601 enum {
602 	RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9,
603 	RK3399_GMAC_PHY_INTF_SEL_MASK  = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
604 	RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
605 	RK3399_GMAC_PHY_INTF_SEL_RMII  = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT),
606 
607 	RK3399_GMAC_CLK_SEL_SHIFT = 4,
608 	RK3399_GMAC_CLK_SEL_MASK  = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
609 	RK3399_GMAC_CLK_SEL_125M  = (0 << RK3399_GMAC_CLK_SEL_SHIFT),
610 	RK3399_GMAC_CLK_SEL_25M	  = (3 << RK3399_GMAC_CLK_SEL_SHIFT),
611 	RK3399_GMAC_CLK_SEL_2_5M  = (2 << RK3399_GMAC_CLK_SEL_SHIFT),
612 };
613 
614 /* GRF_SOC_CON6 */
615 enum {
616 	RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15,
617 	RK3399_RXCLK_DLY_ENA_GMAC_MASK =
618 		(1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
619 	RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
620 	RK3399_RXCLK_DLY_ENA_GMAC_ENABLE =
621 		(1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT),
622 
623 	RK3399_TXCLK_DLY_ENA_GMAC_SHIFT	= 7,
624 	RK3399_TXCLK_DLY_ENA_GMAC_MASK =
625 		(1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
626 	RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
627 	RK3399_TXCLK_DLY_ENA_GMAC_ENABLE =
628 		(1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT),
629 
630 	RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8,
631 	RK3399_CLK_RX_DL_CFG_GMAC_MASK =
632 		(0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT),
633 
634 	RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0,
635 	RK3399_CLK_TX_DL_CFG_GMAC_MASK =
636 		(0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT),
637 };
638 
639 #endif	/* __SOC_ROCKCHIP_RK3399_GRF_H__ */
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