1 /*
2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #ifndef __SOC_ROCKCHIP_RK3399_GRF_H__
8 #define __SOC_ROCKCHIP_RK3399_GRF_H__
9 
10 struct rk3399_grf_regs {
11 	u32 reserved[0x800];
12 	u32 usb3_perf_con0;
13 	u32 usb3_perf_con1;
14 	u32 usb3_perf_con2;
15 	u32 usb3_perf_rd_max_latency_num;
16 	u32 usb3_perf_rd_latency_samp_num;
17 	u32 usb3_perf_rd_latency_acc_num;
18 	u32 usb3_perf_rd_axi_total_byte;
19 	u32 usb3_perf_wr_axi_total_byte;
20 	u32 usb3_perf_working_cnt;
21 	u32 reserved1[0x103];
22 	u32 usb3otg0_con0;
23 	u32 usb3otg0_con1;
24 	u32 reserved2[2];
25 	u32 usb3otg1_con0;
26 	u32 usb3otg1_con1;
27 	u32 reserved3[2];
28 	u32 usb3otg0_status_lat0;
29 	u32 usb3otg0_status_lat1;
30 	u32 usb3otg0_status_cb;
31 	u32 reserved4;
32 	u32 usb3otg1_status_lat0;
33 	u32 usb3otg1_status_lat1;
34 	u32 usb3ogt1_status_cb;
35 	u32 reserved5[0x6e5];
36 	u32 pcie_perf_con0;
37 	u32 pcie_perf_con1;
38 	u32 pcie_perf_con2;
39 	u32 pcie_perf_rd_max_latency_num;
40 	u32 pcie_perf_rd_latency_samp_num;
41 	u32 pcie_perf_rd_laterncy_acc_num;
42 	u32 pcie_perf_rd_axi_total_byte;
43 	u32 pcie_perf_wr_axi_total_byte;
44 	u32 pcie_perf_working_cnt;
45 	u32 reserved6[0x37];
46 	u32 usb20_host0_con0;
47 	u32 usb20_host0_con1;
48 	u32 reserved7[2];
49 	u32 usb20_host1_con0;
50 	u32 usb20_host1_con1;
51 	u32 reserved8[2];
52 	u32 hsic_con0;
53 	u32 hsic_con1;
54 	u32 reserved9[6];
55 	u32 grf_usbhost0_status;
56 	u32 grf_usbhost1_Status;
57 	u32 grf_hsic_status;
58 	u32 reserved10[0xc9];
59 	u32 hsicphy_con0;
60 	u32 reserved11[3];
61 	u32 usbphy0_ctrl[26];
62 	u32 reserved12[6];
63 	u32 usbphy1[26];
64 	u32 reserved13[0x72f];
65 	u32 soc_con9;
66 	u32 reserved14[0x0a];
67 	u32 soc_con20;
68 	u32 soc_con21;
69 	u32 soc_con22;
70 	u32 soc_con23;
71 	u32 soc_con24;
72 	u32 soc_con25;
73 	u32 soc_con26;
74 	u32 reserved15[0xf65];
75 	u32 cpu_con[4];
76 	u32 reserved16[0x1c];
77 	u32 cpu_status[6];
78 	u32 reserved17[0x1a];
79 	u32 a53_perf_con[4];
80 	u32 a53_perf_rd_mon_st;
81 	u32 a53_perf_rd_mon_end;
82 	u32 a53_perf_wr_mon_st;
83 	u32 a53_perf_wr_mon_end;
84 	u32 a53_perf_rd_max_latency_num;
85 	u32 a53_perf_rd_latency_samp_num;
86 	u32 a53_perf_rd_laterncy_acc_num;
87 	u32 a53_perf_rd_axi_total_byte;
88 	u32 a53_perf_wr_axi_total_byte;
89 	u32 a53_perf_working_cnt;
90 	u32 a53_perf_int_status;
91 	u32 reserved18[0x31];
92 	u32 a72_perf_con[4];
93 	u32 a72_perf_rd_mon_st;
94 	u32 a72_perf_rd_mon_end;
95 	u32 a72_perf_wr_mon_st;
96 	u32 a72_perf_wr_mon_end;
97 	u32 a72_perf_rd_max_latency_num;
98 	u32 a72_perf_rd_latency_samp_num;
99 	u32 a72_perf_rd_laterncy_acc_num;
100 	u32 a72_perf_rd_axi_total_byte;
101 	u32 a72_perf_wr_axi_total_byte;
102 	u32 a72_perf_working_cnt;
103 	u32 a72_perf_int_status;
104 	u32 reserved19[0x7f6];
105 	u32 soc_con5;
106 	u32 soc_con6;
107 	u32 reserved20[0x779];
108 	u32 gpio2a_iomux;
109 	union {
110 		u32 iomux_spi2;
111 		u32 gpio2b_iomux;
112 	};
113 	union {
114 		u32 gpio2c_iomux;
115 		u32 iomux_spi5;
116 	};
117 	u32 gpio2d_iomux;
118 	union {
119 		u32 gpio3a_iomux;
120 		u32 iomux_spi0;
121 	};
122 	u32 gpio3b_iomux;
123 	u32 gpio3c_iomux;
124 	union {
125 		u32 iomux_i2s0;
126 		u32 gpio3d_iomux;
127 	};
128 	union {
129 		u32 iomux_i2sclk;
130 		u32 gpio4a_iomux;
131 	};
132 	union {
133 		u32 iomux_sdmmc;
134 		u32 iomux_uart2a;
135 		u32 gpio4b_iomux;
136 	};
137 	union {
138 		u32 iomux_pwm_0;
139 		u32 iomux_pwm_1;
140 		u32 iomux_uart2b;
141 		u32 iomux_uart2c;
142 		u32 iomux_edp_hotplug;
143 		u32 gpio4c_iomux;
144 	};
145 	u32 gpio4d_iomux;
146 	u32 reserved21[4];
147 	u32 gpio2_p[3][4];
148 	u32 reserved22[4];
149 	u32 gpio2_sr[3][4];
150 	u32 reserved23[4];
151 	u32 gpio2_smt[3][4];
152 	u32 reserved24[(0xe130 - 0xe0ec)/4 - 1];
153 	u32 gpio4b_e01;
154 	u32 gpio4b_e2;
155 	u32 reserved24a[(0xe200 - 0xe134)/4 - 1];
156 	u32 soc_con0;
157 	u32 soc_con1;
158 	u32 soc_con2;
159 	u32 soc_con3;
160 	u32 soc_con4;
161 	u32 soc_con5_pcie;
162 	u32 reserved25;
163 	u32 soc_con7;
164 	u32 soc_con8;
165 	u32 soc_con9_pcie;
166 	u32 reserved26[0x1e];
167 	u32 soc_status[6];
168 	u32 reserved27[0x32];
169 	u32 ddrc0_con0;
170 	u32 ddrc0_con1;
171 	u32 ddrc1_con0;
172 	u32 ddrc1_con1;
173 	u32 reserved28[0xac];
174 	u32 io_vsel;
175 	u32 saradc_testbit;
176 	u32 tsadc_testbit_l;
177 	u32 tsadc_testbit_h;
178 	u32 reserved29[0x6c];
179 	u32 chip_id_addr;
180 	u32 reserved30[0x1f];
181 	u32 fast_boot_addr;
182 	u32 reserved31[0x1df];
183 	u32 emmccore_con[12];
184 	u32 reserved32[4];
185 	u32 emmccore_status[4];
186 	u32 reserved33[0x1cc];
187 	u32 emmcphy_con[7];
188 	u32 reserved34;
189 	u32 emmcphy_status;
190 };
191 check_member(rk3399_grf_regs, emmcphy_status, 0xf7a0);
192 
193 struct rk3399_pmugrf_regs {
194 	union {
195 		u32 iomux_pwm_3a;
196 		u32 gpio0a_iomux;
197 	};
198 	u32 gpio0b_iomux;
199 	u32 reserved0[2];
200 	union {
201 		u32 spi1_rxd;
202 		u32 tsadc_int;
203 		u32 gpio1a_iomux;
204 	};
205 	union {
206 		u32 spi1_csclktx;
207 		u32 iomux_pwm_3b;
208 		u32 iomux_i2c0_sda;
209 		u32 gpio1b_iomux;
210 	};
211 	union {
212 		u32 iomux_pwm_2;
213 		u32 iomux_i2c0_scl;
214 		u32 gpio1c_iomux;
215 	};
216 	u32 gpio1d_iomux;
217 	u32 reserved1[8];
218 	u32 gpio0_p[2][4];
219 	u32 reserved3[8];
220 	u32 gpio0a_e;
221 	u32 reserved4;
222 	u32 gpio0b_e;
223 	u32 reserved5[5];
224 	u32 gpio1a_e;
225 	u32 reserved6;
226 	u32 gpio1b_e;
227 	u32 reserved7;
228 	u32 gpio1c_e;
229 	u32 reserved8;
230 	u32 gpio1d_e;
231 	u32 reserved9[0x11];
232 	u32 gpio0l_sr;
233 	u32 reserved10;
234 	u32 gpio1l_sr;
235 	u32 gpio1h_sr;
236 	u32 reserved11[4];
237 	u32 gpio0a_smt;
238 	u32 gpio0b_smt;
239 	u32 reserved12[2];
240 	u32 gpio1a_smt;
241 	u32 gpio1b_smt;
242 	u32 gpio1c_smt;
243 	u32 gpio1d_smt;
244 	u32 reserved13[8];
245 	u32 gpio0l_he;
246 	u32 reserved14;
247 	u32 gpio1l_he;
248 	u32 gpio1h_he;
249 	u32 reserved15[4];
250 	u32 soc_con0;
251 	u32 reserved16[9];
252 	u32 soc_con10;
253 	u32 soc_con11;
254 	u32 reserved17[0x24];
255 	u32 pmupvtm_con0;
256 	u32 pmupvtm_con1;
257 	u32 pmupvtm_status0;
258 	u32 pmupvtm_status1;
259 	u32 grf_osc_e;
260 	u32 reserved18[0x2b];
261 	u32 os_reg0;
262 	u32 os_reg1;
263 	u32 os_reg2;
264 	u32 os_reg3;
265 };
266 check_member(rk3399_pmugrf_regs, os_reg3, 0x30c);
267 
268 struct rk3399_pmusgrf_regs {
269 	u32 ddr_rgn_con[35];
270 	u32 reserved[0x1fe5];
271 	u32 soc_con8;
272 	u32 soc_con9;
273 	u32 soc_con10;
274 	u32 soc_con11;
275 	u32 soc_con12;
276 	u32 soc_con13;
277 	u32 soc_con14;
278 	u32 soc_con15;
279 	u32 reserved1[3];
280 	u32 soc_con19;
281 	u32 soc_con20;
282 	u32 soc_con21;
283 	u32 soc_con22;
284 	u32 reserved2[0x29];
285 	u32 perilp_con[9];
286 	u32 reserved4[7];
287 	u32 perilp_status;
288 	u32 reserved5[0xfaf];
289 	u32 soc_con0;
290 	u32 soc_con1;
291 	u32 reserved6[0x3e];
292 	u32 pmu_con[9];
293 	u32 reserved7[0x17];
294 	u32 fast_boot_addr;
295 	u32 reserved8[0x1f];
296 	u32 efuse_prg_mask;
297 	u32 efuse_read_mask;
298 	u32 reserved9[0x0e];
299 	u32 pmu_slv_con0;
300 	u32 pmu_slv_con1;
301 	u32 reserved10[0x771];
302 	u32 soc_con3;
303 	u32 soc_con4;
304 	u32 soc_con5;
305 	u32 soc_con6;
306 	u32 soc_con7;
307 	u32 reserved11[8];
308 	u32 soc_con16;
309 	u32 soc_con17;
310 	u32 soc_con18;
311 	u32 reserved12[0xdd];
312 	u32 slv_secure_con0;
313 	u32 slv_secure_con1;
314 	u32 reserved13;
315 	u32 slv_secure_con2;
316 	u32 slv_secure_con3;
317 	u32 slv_secure_con4;
318 };
319 check_member(rk3399_pmusgrf_regs, slv_secure_con4, 0xe3d4);
320 
321 enum {
322 	/* GRF_GPIO2B_IOMUX */
323 	GRF_GPIO2B1_SEL_SHIFT	= 0,
324 	GRF_GPIO2B1_SEL_MASK	= 3 << GRF_GPIO2B1_SEL_SHIFT,
325 	GRF_SPI2TPM_RXD		= 1,
326 	GRF_GPIO2B2_SEL_SHIFT	= 2,
327 	GRF_GPIO2B2_SEL_MASK	= 3 << GRF_GPIO2B2_SEL_SHIFT,
328 	GRF_SPI2TPM_TXD		= 1,
329 	GRF_GPIO2B3_SEL_SHIFT	= 6,
330 	GRF_GPIO2B3_SEL_MASK	= 3 << GRF_GPIO2B3_SEL_SHIFT,
331 	GRF_SPI2TPM_CLK		= 1,
332 	GRF_GPIO2B4_SEL_SHIFT	= 8,
333 	GRF_GPIO2B4_SEL_MASK	= 3 << GRF_GPIO2B4_SEL_SHIFT,
334 	GRF_SPI2TPM_CSN0	= 1,
335 
336 	/* GRF_GPIO3A_IOMUX */
337 	GRF_GPIO3A4_SEL_SHIFT	= 8,
338 	GRF_GPIO3A4_SEL_MASK	= 3 << GRF_GPIO3A4_SEL_SHIFT,
339 	GRF_SPI0NORCODEC_RXD	= 2,
340 	GRF_GPIO3A5_SEL_SHIFT	= 10,
341 	GRF_GPIO3A5_SEL_MASK	= 3 << GRF_GPIO3A5_SEL_SHIFT,
342 	GRF_SPI0NORCODEC_TXD	= 2,
343 	GRF_GPIO3A6_SEL_SHIFT	= 12,
344 	GRF_GPIO3A6_SEL_MASK	= 3 << GRF_GPIO3A6_SEL_SHIFT,
345 	GRF_SPI0NORCODEC_CLK	= 2,
346 	GRF_GPIO3A7_SEL_SHIFT	= 14,
347 	GRF_GPIO3A7_SEL_MASK	= 3 << GRF_GPIO3A7_SEL_SHIFT,
348 	GRF_SPI0NORCODEC_CSN0	= 2,
349 
350 	/* GRF_GPIO3B_IOMUX */
351 	GRF_GPIO3B0_SEL_SHIFT	= 0,
352 	GRF_GPIO3B0_SEL_MASK	= 3 << GRF_GPIO3B0_SEL_SHIFT,
353 	GRF_SPI0NORCODEC_CSN1	= 2,
354 
355 	/* GRF_GPIO4B_IOMUX */
356 	GRF_GPIO4B0_SEL_SHIFT	= 0,
357 	GRF_GPIO4B0_SEL_MASK	= 3 << GRF_GPIO4B0_SEL_SHIFT,
358 	GRF_SDMMC_DATA0		= 1,
359 	GRF_UART2DBGA_SIN	= 2,
360 	GRF_GPIO4B1_SEL_SHIFT	= 2,
361 	GRF_GPIO4B1_SEL_MASK	= 3 << GRF_GPIO4B1_SEL_SHIFT,
362 	GRF_SDMMC_DATA1		= 1,
363 	GRF_UART2DBGA_SOUT	= 2,
364 	GRF_GPIO4B2_SEL_SHIFT	= 4,
365 	GRF_GPIO4B2_SEL_MASK	= 3 << GRF_GPIO4B2_SEL_SHIFT,
366 	GRF_SDMMC_DATA2		= 1,
367 	GRF_GPIO4B3_SEL_SHIFT	= 6,
368 	GRF_GPIO4B3_SEL_MASK	= 3 << GRF_GPIO4B3_SEL_SHIFT,
369 	GRF_SDMMC_DATA3		= 1,
370 	GRF_GPIO4B4_SEL_SHIFT	= 8,
371 	GRF_GPIO4B4_SEL_MASK    = 3 << GRF_GPIO4B4_SEL_SHIFT,
372 	GRF_SDMMC_CLKOUT        = 1,
373 	GRF_GPIO4B5_SEL_SHIFT   = 10,
374 	GRF_GPIO4B5_SEL_MASK    = 3 << GRF_GPIO4B5_SEL_SHIFT,
375 	GRF_SDMMC_CMD           = 1,
376 
377 	/*  GRF_GPIO4C_IOMUX */
378 	GRF_GPIO4C0_SEL_SHIFT   = 0,
379 	GRF_GPIO4C0_SEL_MASK    = 3 << GRF_GPIO4C0_SEL_SHIFT,
380 	GRF_UART2DGBB_SIN       = 2,
381 	GRF_GPIO4C1_SEL_SHIFT   = 2,
382 	GRF_GPIO4C1_SEL_MASK    = 3 << GRF_GPIO4C1_SEL_SHIFT,
383 	GRF_UART2DGBB_SOUT      = 2,
384 	GRF_GPIO4C2_SEL_SHIFT   = 4,
385 	GRF_GPIO4C2_SEL_MASK    = 3 << GRF_GPIO4C2_SEL_SHIFT,
386 	GRF_PWM_0               = 1,
387 	GRF_GPIO4C3_SEL_SHIFT   = 6,
388 	GRF_GPIO4C3_SEL_MASK    = 3 << GRF_GPIO4C3_SEL_SHIFT,
389 	GRF_UART2DGBC_SIN       = 1,
390 	GRF_GPIO4C4_SEL_SHIFT   = 8,
391 	GRF_GPIO4C4_SEL_MASK    = 3 << GRF_GPIO4C4_SEL_SHIFT,
392 	GRF_UART2DBGC_SOUT      = 1,
393 	GRF_GPIO4C6_SEL_SHIFT   = 12,
394 	GRF_GPIO4C6_SEL_MASK    = 3 << GRF_GPIO4C6_SEL_SHIFT,
395 	GRF_PWM_1               = 1,
396 
397 	/* GRF_SOC_CON7 */
398 	GRF_UART_DBG_SEL_SHIFT	= 10,
399 	GRF_UART_DBG_SEL_MASK	= 3 << GRF_UART_DBG_SEL_SHIFT,
400 	GRF_UART_DBG_SEL_C	= 2,
401 
402 	/*  PMUGRF_GPIO0A_IOMUX */
403 	PMUGRF_GPIO0A6_SEL_SHIFT        = 12,
404 	PMUGRF_GPIO0A6_SEL_MASK = 3 << PMUGRF_GPIO0A6_SEL_SHIFT,
405 	PMUGRF_PWM_3A           = 1,
406 
407 	/*  PMUGRF_GPIO1A_IOMUX */
408 	PMUGRF_GPIO1A7_SEL_SHIFT        = 14,
409 	PMUGRF_GPIO1A7_SEL_MASK = 3 << PMUGRF_GPIO1A7_SEL_SHIFT,
410 	PMUGRF_SPI1EC_RXD       = 2,
411 
412 	/*  PMUGRF_GPIO1B_IOMUX */
413 	PMUGRF_GPIO1B0_SEL_SHIFT        = 0,
414 	PMUGRF_GPIO1B0_SEL_MASK = 3 << PMUGRF_GPIO1B0_SEL_SHIFT,
415 	PMUGRF_SPI1EC_TXD       = 2,
416 	PMUGRF_GPIO1B1_SEL_SHIFT        = 2,
417 	PMUGRF_GPIO1B1_SEL_MASK = 3 << PMUGRF_GPIO1B1_SEL_SHIFT,
418 	PMUGRF_SPI1EC_CLK       = 2,
419 	PMUGRF_GPIO1B2_SEL_SHIFT        = 4,
420 	PMUGRF_GPIO1B2_SEL_MASK = 3 << PMUGRF_GPIO1B2_SEL_SHIFT,
421 	PMUGRF_SPI1EC_CSN0      = 2,
422 	PMUGRF_GPIO1B6_SEL_SHIFT        = 12,
423 	PMUGRF_GPIO1B6_SEL_MASK = 3 << PMUGRF_GPIO1B6_SEL_SHIFT,
424 	PMUGRF_PWM_3B           = 1,
425 	PMUGRF_GPIO1B7_SEL_SHIFT        = 14,
426 	PMUGRF_GPIO1B7_SEL_MASK = 3 << PMUGRF_GPIO1B7_SEL_SHIFT,
427 	PMUGRF_I2C0PMU_SDA      = 2,
428 
429 	/*  PMUGRF_GPIO1C_IOMUX */
430 	PMUGRF_GPIO1C0_SEL_SHIFT        = 0,
431 	PMUGRF_GPIO1C0_SEL_MASK = 3 << PMUGRF_GPIO1C0_SEL_SHIFT,
432 	PMUGRF_I2C0PMU_SCL      = 2,
433 	PMUGRF_GPIO1C3_SEL_SHIFT        = 6,
434 	PMUGRF_GPIO1C3_SEL_MASK = 3 << PMUGRF_GPIO1C3_SEL_SHIFT,
435 	PMUGRF_PWM_2            = 1,
436 
437 };
438 
439 #endif	/* __SOC_ROCKCHIP_RK3399_GRF_H__ */
440