1 /* (C) Copyright 2016 Rockchip Electronics Co., Ltd
2  *
3  * SPDX-License-Identifier:     GPL-2.0+
4  */
5 #ifndef _ASM_ARCH_GRF_RK3368_H
6 #define _ASM_ARCH_GRF_RK3368_H
7 
8 #include <common.h>
9 
10 struct rk3368_grf {
11 	u32 gpio1a_iomux;
12 	u32 gpio1b_iomux;
13 	u32 gpio1c_iomux;
14 	u32 gpio1d_iomux;
15 	u32 gpio2a_iomux;
16 	u32 gpio2b_iomux;
17 	u32 gpio2c_iomux;
18 	u32 gpio2d_iomux;
19 	u32 gpio3a_iomux;
20 	u32 gpio3b_iomux;
21 	u32 gpio3c_iomux;
22 	u32 gpio3d_iomux;
23 	u32 reserved[0x34];
24 	u32 gpio1a_pull;
25 	u32 gpio1b_pull;
26 	u32 gpio1c_pull;
27 	u32 gpio1d_pull;
28 	u32 gpio2a_pull;
29 	u32 gpio2b_pull;
30 	u32 gpio2c_pull;
31 	u32 gpio2d_pull;
32 	u32 gpio3a_pull;
33 	u32 gpio3b_pull;
34 	u32 gpio3c_pull;
35 	u32 gpio3d_pull;
36 	u32 reserved1[0x34];
37 	u32 gpio1a_drv;
38 	u32 gpio1b_drv;
39 	u32 gpio1c_drv;
40 	u32 gpio1d_drv;
41 	u32 gpio2a_drv;
42 	u32 gpio2b_drv;
43 	u32 gpio2c_drv;
44 	u32 gpio2d_drv;
45 	u32 gpio3a_drv;
46 	u32 gpio3b_drv;
47 	u32 gpio3c_drv;
48 	u32 gpio3d_drv;
49 	u32 reserved2[0x34];
50 	u32 gpio1l_sr;
51 	u32 gpio1h_sr;
52 	u32 gpio2l_sr;
53 	u32 gpio2h_sr;
54 	u32 gpio3l_sr;
55 	u32 gpio3h_sr;
56 	u32 reserved3[0x1a];
57 	u32 gpio_smt;
58 	u32 reserved4[0x1f];
59 	u32 soc_con0;
60 	u32 soc_con1;
61 	u32 soc_con2;
62 	u32 soc_con3;
63 	u32 soc_con4;
64 	u32 soc_con5;
65 	u32 soc_con6;
66 	u32 soc_con7;
67 	u32 soc_con8;
68 	u32 soc_con9;
69 	u32 soc_con10;
70 	u32 soc_con11;
71 	u32 soc_con12;
72 	u32 soc_con13;
73 	u32 soc_con14;
74 	u32 soc_con15;
75 	u32 soc_con16;
76 	u32 soc_con17;
77 };
78 check_member(rk3368_grf, soc_con17, 0x444);
79 
80 struct rk3368_pmu_grf {
81 	u32 gpio0a_iomux;
82 	u32 gpio0b_iomux;
83 	u32 gpio0c_iomux;
84 	u32 gpio0d_iomux;
85 	u32 gpio0a_pull;
86 	u32 gpio0b_pull;
87 	u32 gpio0c_pull;
88 	u32 gpio0d_pull;
89 	u32 gpio0a_drv;
90 	u32 gpio0b_drv;
91 	u32 gpio0c_drv;
92 	u32 gpio0d_drv;
93 	u32 gpio0l_sr;
94 	u32 gpio0h_sr;
95 };
96 check_member(rk3368_pmu_grf, gpio0h_sr, 0x34);
97 
98 /*GRF_GPIO0C_IOMUX*/
99 enum {
100 	GPIO0C7_SHIFT		= 14,
101 	GPIO0C7_MASK		= 3 << GPIO0C7_SHIFT,
102 	GPIO0C7_GPIO		= 0,
103 	GPIO0C7_LCDC_D19,
104 	GPIO0C7_TRACE_D9,
105 	GPIO0C7_UART1_RTSN,
106 
107 	GPIO0C6_SHIFT           = 12,
108 	GPIO0C6_MASK            = 3 << GPIO0C6_SHIFT,
109 	GPIO0C6_GPIO            = 0,
110 	GPIO0C6_LCDC_D18,
111 	GPIO0C6_TRACE_D8,
112 	GPIO0C6_UART1_CTSN,
113 
114 	GPIO0C5_SHIFT           = 10,
115 	GPIO0C5_MASK            = 3 << GPIO0C5_SHIFT,
116 	GPIO0C5_GPIO            = 0,
117 	GPIO0C5_LCDC_D17,
118 	GPIO0C5_TRACE_D7,
119 	GPIO0C5_UART1_SOUT,
120 
121 	GPIO0C4_SHIFT           = 8,
122 	GPIO0C4_MASK            = 3 << GPIO0C4_SHIFT,
123 	GPIO0C4_GPIO            = 0,
124 	GPIO0C4_LCDC_D16,
125 	GPIO0C4_TRACE_D6,
126 	GPIO0C4_UART1_SIN,
127 
128 	GPIO0C3_SHIFT           = 6,
129 	GPIO0C3_MASK            = 3 << GPIO0C3_SHIFT,
130 	GPIO0C3_GPIO            = 0,
131 	GPIO0C3_LCDC_D15,
132 	GPIO0C3_TRACE_D5,
133 	GPIO0C3_MCU_JTAG_TDO,
134 
135 	GPIO0C2_SHIFT           = 4,
136 	GPIO0C2_MASK            = 3 << GPIO0C2_SHIFT,
137 	GPIO0C2_GPIO            = 0,
138 	GPIO0C2_LCDC_D14,
139 	GPIO0C2_TRACE_D4,
140 	GPIO0C2_MCU_JTAG_TDI,
141 
142 	GPIO0C1_SHIFT           = 2,
143 	GPIO0C1_MASK            = 3 << GPIO0C1_SHIFT,
144 	GPIO0C1_GPIO            = 0,
145 	GPIO0C1_LCDC_D13,
146 	GPIO0C1_TRACE_D3,
147 	GPIO0C1_MCU_JTAG_TRTSN,
148 
149 	GPIO0C0_SHIFT           = 0,
150 	GPIO0C0_MASK            = 3 << GPIO0C0_SHIFT,
151 	GPIO0C0_GPIO            = 0,
152 	GPIO0C0_LCDC_D12,
153 	GPIO0C0_TRACE_D2,
154 	GPIO0C0_MCU_JTAG_TDO,
155 };
156 
157 /*GRF_GPIO0D_IOMUX*/
158 enum {
159 	GPIO0D7_SHIFT           = 14,
160 	GPIO0D7_MASK            = 3 << GPIO0D7_SHIFT,
161 	GPIO0D7_GPIO            = 0,
162 	GPIO0D7_LCDC_DCLK,
163 	GPIO0D7_TRACE_CTL,
164 	GPIO0D7_PMU_DEBUG5,
165 
166 	GPIO0D6_SHIFT           = 12,
167 	GPIO0D6_MASK            = 3 << GPIO0D6_SHIFT,
168 	GPIO0D6_GPIO            = 0,
169 	GPIO0D6_LCDC_DEN,
170 	GPIO0D6_TRACE_CLK,
171 	GPIO0D6_PMU_DEBUG4,
172 
173 	GPIO0D5_SHIFT           = 10,
174 	GPIO0D5_MASK            = 3 << GPIO0D5_SHIFT,
175 	GPIO0D5_GPIO            = 0,
176 	GPIO0D5_LCDC_VSYNC,
177 	GPIO0D5_TRACE_D15,
178 	GPIO0D5_PMU_DEBUG3,
179 
180 	GPIO0D4_SHIFT           = 8,
181 	GPIO0D4_MASK            = 3 << GPIO0D4_SHIFT,
182 	GPIO0D4_GPIO            = 0,
183 	GPIO0D4_LCDC_HSYNC,
184 	GPIO0D4_TRACE_D14,
185 	GPIO0D4_PMU_DEBUG2,
186 
187 	GPIO0D3_SHIFT           = 6,
188 	GPIO0D3_MASK            = 3 << GPIO0D3_SHIFT,
189 	GPIO0D3_GPIO            = 0,
190 	GPIO0D3_LCDC_D23,
191 	GPIO0D3_TRACE_D13,
192 	GPIO0D3_UART4_SIN,
193 
194 	GPIO0D2_SHIFT           = 4,
195 	GPIO0D2_MASK            = 3 << GPIO0D2_SHIFT,
196 	GPIO0D2_GPIO            = 0,
197 	GPIO0D2_LCDC_D22,
198 	GPIO0D2_TRACE_D12,
199 	GPIO0D2_UART4_SOUT,
200 
201 	GPIO0D1_SHIFT           = 2,
202 	GPIO0D1_MASK            = 3 << GPIO0D1_SHIFT,
203 	GPIO0D1_GPIO            = 0,
204 	GPIO0D1_LCDC_D21,
205 	GPIO0D1_TRACE_D11,
206 	GPIO0D1_UART4_RTSN,
207 
208 	GPIO0D0_SHIFT           = 0,
209 	GPIO0D0_MASK            = 3 << GPIO0D0_SHIFT,
210 	GPIO0D0_GPIO            = 0,
211 	GPIO0D0_LCDC_D20,
212 	GPIO0D0_TRACE_D10,
213 	GPIO0D0_UART4_CTSN,
214 };
215 
216 /*GRF_GPIO2A_IOMUX*/
217 enum {
218 	GPIO2A7_SHIFT           = 14,
219 	GPIO2A7_MASK            = 3 << GPIO2A7_SHIFT,
220 	GPIO2A7_GPIO            = 0,
221 	GPIO2A7_SDMMC0_D2,
222 	GPIO2A7_JTAG_TCK,
223 
224 	GPIO2A6_SHIFT           = 12,
225 	GPIO2A6_MASK            = 3 << GPIO2A6_SHIFT,
226 	GPIO2A6_GPIO            = 0,
227 	GPIO2A6_SDMMC0_D1,
228 	GPIO2A6_UART2_SIN,
229 
230 	GPIO2A5_SHIFT           = 10,
231 	GPIO2A5_MASK            = 3 << GPIO2A5_SHIFT,
232 	GPIO2A5_GPIO            = 0,
233 	GPIO2A5_SDMMC0_D0,
234 	GPIO2A5_UART2_SOUT,
235 
236 	GPIO2A4_SHIFT           = 8,
237 	GPIO2A4_MASK            = 3 << GPIO2A4_SHIFT,
238 	GPIO2A4_GPIO            = 0,
239 	GPIO2A4_FLASH_DQS,
240 	GPIO2A4_EMMC_CLKO,
241 
242 	GPIO2A3_SHIFT           = 6,
243 	GPIO2A3_MASK            = 3 << GPIO2A3_SHIFT,
244 	GPIO2A3_GPIO            = 0,
245 	GPIO2A3_FLASH_CSN3,
246 	GPIO2A3_EMMC_RSTNO,
247 
248 	GPIO2A2_SHIFT           = 4,
249 	GPIO2A2_MASK            = 3 << GPIO2A2_SHIFT,
250 	GPIO2A2_GPIO           = 0,
251 	GPIO2A2_FLASH_CSN2,
252 
253 	GPIO2A1_SHIFT           = 2,
254 	GPIO2A1_MASK            = 3 << GPIO2A1_SHIFT,
255 	GPIO2A1_GPIO            = 0,
256 	GPIO2A1_FLASH_CSN1,
257 
258 	GPIO2A0_SHIFT           = 0,
259 	GPIO2A0_MASK            = 3 << GPIO2A0_SHIFT,
260 	GPIO2A0_GPIO            = 0,
261 	GPIO2A0_FLASH_CSN0,
262 };
263 
264 /*GRF_GPIO2D_IOMUX*/
265 enum {
266 	GPIO2D7_SHIFT           = 14,
267 	GPIO2D7_MASK            = 3 << GPIO2D7_SHIFT,
268 	GPIO2D7_GPIO            = 0,
269 	GPIO2D7_SDIO0_D3,
270 
271 	GPIO2D6_SHIFT           = 12,
272 	GPIO2D6_MASK            = 3 << GPIO2D6_SHIFT,
273 	GPIO2D6_GPIO            = 0,
274 	GPIO2D6_SDIO0_D2,
275 
276 	GPIO2D5_SHIFT           = 10,
277 	GPIO2D5_MASK            = 3 << GPIO2D5_SHIFT,
278 	GPIO2D5_GPIO            = 0,
279 	GPIO2D5_SDIO0_D1,
280 
281 	GPIO2D4_SHIFT           = 8,
282 	GPIO2D4_MASK            = 3 << GPIO2D4_SHIFT,
283 	GPIO2D4_GPIO            = 0,
284 	GPIO2D4_SDIO0_D0,
285 
286 	GPIO2D3_SHIFT           = 6,
287 	GPIO2D3_MASK            = 3 << GPIO2D3_SHIFT,
288 	GPIO2D3_GPIO            = 0,
289 	GPIO2D3_UART0_RTS0,
290 
291 	GPIO2D2_SHIFT           = 4,
292 	GPIO2D2_MASK            = 3 << GPIO2D2_SHIFT,
293 	GPIO2D2_GPIO            = 0,
294 	GPIO2D2_UART0_CTS0,
295 
296 	GPIO2D1_SHIFT           = 2,
297 	GPIO2D1_MASK            = 3 << GPIO2D1_SHIFT,
298 	GPIO2D1_GPIO            = 0,
299 	GPIO2D1_UART0_SOUT,
300 
301 	GPIO2D0_SHIFT           = 0,
302 	GPIO2D0_MASK            = 3 << GPIO2D0_SHIFT,
303 	GPIO2D0_GPIO            = 0,
304 	GPIO2D0_UART0_SIN,
305 };
306 
307 /*GRF_GPIO3C_IOMUX*/
308 enum {
309 	GPIO3C7_SHIFT           = 14,
310 	GPIO3C7_MASK            = 3 << GPIO3C7_SHIFT,
311 	GPIO3C7_GPIO            = 0,
312 	GPIO3C7_EDPHDMI_CECINOUT,
313 	GPIO3C7_ISP_FLASHTRIGIN,
314 
315 	GPIO3C6_SHIFT           = 12,
316 	GPIO3C6_MASK            = 3 << GPIO3C6_SHIFT,
317 	GPIO3C6_GPIO            = 0,
318 	GPIO3C6_MAC_CLK,
319 	GPIO3C6_ISP_SHUTTERTRIG,
320 
321 	GPIO3C5_SHIFT           = 10,
322 	GPIO3C5_MASK            = 3 << GPIO3C5_SHIFT,
323 	GPIO3C5_GPIO            = 0,
324 	GPIO3C5_MAC_RXER,
325 	GPIO3C5_ISP_PRELIGHTTRIG,
326 
327 	GPIO3C4_SHIFT           = 8,
328 	GPIO3C4_MASK            = 3 << GPIO3C4_SHIFT,
329 	GPIO3C4_GPIO            = 0,
330 	GPIO3C4_MAC_RXDV,
331 	GPIO3C4_ISP_FLASHTRIGOUT,
332 
333 	GPIO3C3_SHIFT           = 6,
334 	GPIO3C3_MASK            = 3 << GPIO3C3_SHIFT,
335 	GPIO3C3_GPIO            = 0,
336 	GPIO3C3_MAC_RXDV,
337 	GPIO3C3_EMMC_RSTNO,
338 
339 	GPIO3C2_SHIFT           = 4,
340 	GPIO3C2_MASK            = 3 << GPIO3C2_SHIFT,
341 	GPIO3C2_MAC_MDC            = 0,
342 	GPIO3C2_ISP_SHUTTEREN,
343 
344 	GPIO3C1_SHIFT           = 2,
345 	GPIO3C1_MASK            = 3 << GPIO3C1_SHIFT,
346 	GPIO3C1_GPIO            = 0,
347 	GPIO3C1_MAC_RXD2,
348 	GPIO3C1_UART3_RTSN,
349 
350 	GPIO3C0_SHIFT           = 0,
351 	GPIO3C0_MASK            = 3 << GPIO3C0_SHIFT,
352 	GPIO3C0_GPIO            = 0,
353 	GPIO3C0_MAC_RXD1,
354 	GPIO3C0_UART3_CTSN,
355 	GPIO3C0_GPS_RFCLK,
356 };
357 
358 /*GRF_GPIO3D_IOMUX*/
359 enum {
360 	GPIO3D7_SHIFT           = 14,
361 	GPIO3D7_MASK            = 3 << GPIO3D7_SHIFT,
362 	GPIO3D7_GPIO            = 0,
363 	GPIO3D7_SC_VCC18V,
364 	GPIO3D7_I2C2_SDA,
365 	GPIO3D7_GPUJTAG_TCK,
366 
367 	GPIO3D6_SHIFT           = 12,
368 	GPIO3D6_MASK            = 3 << GPIO3D6_SHIFT,
369 	GPIO3D6_GPIO            = 0,
370 	GPIO3D6_IR_TX,
371 	GPIO3D6_UART3_SOUT,
372 	GPIO3D6_PWM3,
373 
374 	GPIO3D5_SHIFT           = 10,
375 	GPIO3D5_MASK            = 3 << GPIO3D5_SHIFT,
376 	GPIO3D5_GPIO            = 0,
377 	GPIO3D5_IR_RX,
378 	GPIO3D5_UART3_SIN,
379 
380 	GPIO3D4_SHIFT           = 8,
381 	GPIO3D4_MASK            = 3 << GPIO3D4_SHIFT,
382 	GPIO3D4_GPIO            = 0,
383 	GPIO3D4_MAC_TXCLKOUT,
384 	GPIO3D4_SPI1_CSN1,
385 
386 	GPIO3D3_SHIFT           = 6,
387 	GPIO3D3_MASK            = 3 << GPIO3D3_SHIFT,
388 	GPIO3D3_GPIO            = 0,
389 	GPIO3D3_HDMII2C_SCL,
390 	GPIO3D3_I2C5_SCL,
391 
392 	GPIO3D2_SHIFT           = 4,
393 	GPIO3D2_MASK            = 3 << GPIO3D2_SHIFT,
394 	GPIO3D2_GPIO            = 0,
395 	GPIO3D2_HDMII2C_SDA,
396 	GPIO3D2_I2C5_SDA,
397 
398 	GPIO3D1_SHIFT           = 2,
399 	GPIO3D1_MASK            = 3 << GPIO3D1_SHIFT,
400 	GPIO3D1_GPIO            = 0,
401 	GPIO3D1_MAC_RXCLKIN,
402 	GPIO3D1_I2C4_SCL,
403 
404 	GPIO3D0_SHIFT           = 0,
405 	GPIO3D0_MASK            = 3 << GPIO3D0_SHIFT,
406 	GPIO3D0_GPIO            = 0,
407 	GPIO3D0_MAC_MDIO,
408 	GPIO3D0_I2C4_SDA,
409 };
410 
411 /*GRF_SOC_CON11/12/13*/
412 enum {
413 	MCU_SRAM_BASE_BIT27_BIT12_SHIFT	= 0,
414 	MCU_SRAM_BASE_BIT27_BIT12_MASK	= GENMASK(15, 0),
415 };
416 
417 /*GRF_SOC_CON12*/
418 enum {
419 	MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT  = 0,
420 	MCU_EXSRAM_BASE_BIT27_BIT12_MASK   = GENMASK(15, 0),
421 };
422 
423 /*GRF_SOC_CON13*/
424 enum {
425 	MCU_EXPERI_BASE_BIT27_BIT12_SHIFT  = 0,
426 	MCU_EXPERI_BASE_BIT27_BIT12_MASK   = GENMASK(15, 0),
427 };
428 
429 /*GRF_SOC_CON14*/
430 enum {
431 	MCU_EXPERI_BASE_BIT31_BIT28_SHIFT	= 12,
432 	MCU_EXPERI_BASE_BIT31_BIT28_MASK	= GENMASK(15, 12),
433 	MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT	= 8,
434 	MCU_EXSRAM_BASE_BIT31_BIT28_MASK	= GENMASK(11, 8),
435 	MCU_SRAM_BASE_BIT31_BIT28_SHIFT		= 4,
436 	MCU_SRAM_BASE_BIT31_BIT28_MASK		= GENMASK(7, 4),
437 	MCU_CODE_BASE_BIT31_BIT28_SHIFT		= 0,
438 	MCU_CODE_BASE_BIT31_BIT28_MASK		= GENMASK(3, 0),
439 };
440 #endif
441